Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules

This paper presents Maverick, a proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target partial reconfiguration (PR) regions in field-programmable gate array (FPGA) designs. After an initial static design and PR region are created with Xilinx's Vivado PR flow, the Maverick flow can then compile and configure RMs onto that PR region—without the use of vendor tools. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. This paper describes the Maverick flow and shows the results of it running on a PYNQ-Z1's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

[1]  Sen Wang,et al.  VTR 7.0: Next Generation Architecture and CAD System for FPGAs , 2014, TRETS.

[2]  Kizheppatt Vipin,et al.  FPGA Dynamic and Partial Reconfiguration , 2018, ACM Comput. Surv..

[3]  Vaughn Betz,et al.  A fast routability-driven router for FPGAs , 1998, FPGA '98.

[4]  Chris Lavin,et al.  RapidWright: Enabling Custom Crafted Implementations for FPGAs , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[5]  Michael Hutter,et al.  EM-based detection of hardware trojans on FPGAs , 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[6]  Michael J. Wirthlin,et al.  Improving the Effectiveness of TMR Designs on FPGAs with SEU-Aware Incremental Placement , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[7]  Brent E. Nelson,et al.  RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs , 2015, FPGA.

[8]  Carl Ebeling,et al.  Placement and routing tools for the Triptych FPGA , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Dirk Koch,et al.  Partial Reconfiguration on FPGAs - Architectures, Tools and Applications , 2012, Lecture Notes in Electrical Engineering.

[10]  Brad White.  Tincr: Integrating Custom CAD Tool Frameworks with the Xilinx Vivado Design Suite , 2014 .

[11]  Eddie Hung.  Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[12]  Peter M. Athanas,et al.  Torc: towards an open-source tool flow , 2011, FPGA '11.

[13]  Brent E. Nelson,et al.  Packing a modern Xilinx FPGA using RapidSmith , 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

[14]  Brent E. Nelson.  Third Party CAD Tools for FPGA Design - A Survey of the Current Landscape , 2019, ARC.

[15]  Jeffrey B. Goeders,et al.  Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[16]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[17]  Andreas Traber,et al.  Preemptive Hardware Multitasking in ReconOS , 2015, ARC.

[18]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.

[19]  Brent E. Nelson,et al.  Tincr — A custom CAD tool framework for Vivado , 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

[20]  Neil Joseph Steiner.  Autonomous Computing Systems , 2008 .

[21]  Sándor P. Fekete,et al.  Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments , 2017, 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[22]  Brent E. Nelson,et al.  RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[23]  Aaron Gerald Stoddard.  Configuration Scrubbing Architectures for High-Reliability FPGA Systems , 2015 .

[24]  Nils J. Nilsson,et al.  A Formal Basis for the Heuristic Determination of Minimum Cost Paths , 1968, IEEE Trans. Syst. Sci. Cybern..

[25]  Thomas James Townsend.  Vivado Design Interface: Enabling CAD-Tool Design for Next Generation Xilinx FPGA Devices , 2017 .

[26]  Brent E. Nelson,et al.  Vivado design interface: An export/import capability for Vivado FPGA designs , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

[27]  Jordan S. Swartz.  A High-Speed Timing-Aware Router for FPGAs , 1998 .

[28]  Vaughn Betz,et al.  The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[29]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[30]  Travis D. Haroldsen.  Academic Packing for Commercial FPGA Architectures , 2017 .