A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors

This paper presents a circuit design of a Ternary Content-Addressable Memory (TCAM) using Single- Electron Transistors (SETs). The proposed TCAM cell employs a SET-based ternary memory and a dual-gate SET for ternary data matching. The multi-level functionality of SET is fully utilized to reduce circuit complexity. Basic matching operation of the TCAM cell is verified using a multi-gate SET and a MOSFET fabricated on the same Silicon-On-Insulator (SOI) wafer by Pattern-Dependent OXidation (PADOX) process.

[1]  T. Hiramoto,et al.  Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[2]  Hiroshi Inokawa,et al.  A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic( New System Paradigms for Integrated Electronics) , 2004 .

[3]  Hiroshi Inokawa,et al.  Silicon single-electron devices , 2002 .

[4]  Hiroshi Inokawa,et al.  A single-electron-transistor logic gate family and its application - Part I: basic components for binary, multiple-valued and mixed-mode logic , 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

[5]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[6]  H. Inokawa,et al.  A compact analytical model for asymmetric single-electron tunneling transistors , 2003 .

[7]  Yasuo Takahashi,et al.  Size dependence of the characteristics of Si single-electron transistors on SIMOX substrates , 1996 .

[8]  Yasuo Takahashi,et al.  Multigate single-electron transistors and their application to an exclusive-OR gate , 2000 .

[9]  Hiroshi Inokawa,et al.  A single-electron-transistor logic gate family and its application - Part II: design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions , 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

[10]  Hiroshi Inokawa,et al.  A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter , 2004 .

[11]  H. Inokawa,et al.  Room-temperature single-electron transfer and detection with silicon nanodevices , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[12]  Hiroshi Inokawa,et al.  A two-bit-per-cell content-addressable memory using single-electron transistors , 2005, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).

[13]  Yasuo Takahashi,et al.  A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors , 2003 .