CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.

[1]  Yuan Taur,et al.  Scaling of Nanowire Transistors , 2008, IEEE Transactions on Electron Devices.

[2]  Richard M. Swanson,et al.  Modelling of minority-carrier transport in heavily doped silicon emitters , 1987 .

[3]  Characteristic Features of 1-D Ballistic Transport in Nanowire MOSFETs , 2008, IEEE Transactions on Nanotechnology.

[4]  Gerhard Klimeck,et al.  Valence band effective-mass expressions in the sp 3 d 5 s * empirical tight-binding model applied to a Si and Ge parametrization , 2004 .

[5]  Scott E. Thompson,et al.  Strain effects on three-dimensional, two-dimensional, and one-dimensional silicon logic devices: Predicting the future of strained silicon , 2010 .

[6]  D. Vasileska,et al.  Diffusive transport in quasi-2D and quasi-1D electron systems , 2008, 0811.1937.

[7]  J. Hauser.  Noise margin criteria for digital logic circuits , 1993 .

[8]  Phil Oldiges,et al.  Simulation of phonon-induced mobility under arbitrary stress , wafer and channel orientations and its application to FinFET technology , 2013 .

[9]  Massimo Vanzi,et al.  A physically based mobility model for numerical simulation of nonplanar devices , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  K. Natori.  Compact Modeling of Quasi-Ballistic Silicon Nanowire MOSFETs , 2012, IEEE Transactions on Electron Devices.

[11]  Dim-Lee Kwong,et al.  Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach , 2008 .

[12]  S. A. Mujtaba.  ADVANCED MOBILITY MODELS FOR DESIGN AND SIMULATION OF DEEP SUBMICROMETER MOSFETS , 1995 .

[13]  Jiang Yan,et al.  High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible Process , 2010, IEEE Electron Device Letters.

[14]  D. Klaassen,et al.  A new recombination model for device simulation including tunneling , 1992 .

[15]  T. Numata,et al.  SPICE-Based Performance Analysis of Trigate Silicon Nanowire CMOS Circuits , 2013, IEEE Transactions on Electron Devices.

[16]  Sylvain Barraud,et al.  Enhanced Performance of P-FET Omega-Gate SoI Nanowire With Recessed-SiGe Source-Drain Down to 13-nm Gate Length , 2013, IEEE Electron Device Letters.

[17]  Hiroshi Iwai,et al.  Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits , 2014 .

[18]  D. A. Antoniadis,et al.  Room-temperature carrier transport in high-performance short-channel Silicon nanowire MOSFETs , 2012, 2012 International Electron Devices Meeting.

[19]  P. Woerlee,et al.  A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions , 1994 .

[20]  Jean-Pierre Colinge,et al.  Device design guidelines for nano-scale MuGFETs , 2007 .

[21]  G. Cohen,et al.  High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[22]  MeiKei Ieong,et al.  Efficient Quantum Correction Model for Multi-dimensional CMOS Simulations , 1998 .

[23]  Gernot Heiser,et al.  Three-dimensional numerical semiconductor device simulation: algorithms, architectures, results , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Meikei Ieong,et al.  Technology modeling for emerging SOI devices , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.

[25]  Gerhard Klimeck,et al.  Bandstructure and orientation effects in ballistic Si and Ge nanowire FETs , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[26]  Kenji Natori.  The capacitance of microstructures , 1995 .

[27]  Jack A. Mandelman,et al.  Technology CAD at IBM , 1993 .

[28]  G. Paasch,et al.  A Modified Local Density Approximation. Electron Density in Inversion Layers , 1982 .