论文信息 - Feasibility study of 70nm pitch Cu/porous low-k D/D integration featuring EUV lithography toward 22nm generation

Feasibility study of 70nm pitch Cu/porous low-k D/D integration featuring EUV lithography toward 22nm generation

A feasibility study of 70 nm pitch 2-level dual damascene interconnects featuring EUV lithography is presented. Using Ru barrier metal and scalable porous silica (Po-SiO, k=2.1), a low resistivity below 4.5 µΩcm and a 13 % reduction in wiring capacitance compared with porous SiOC (k=2.65) was obtained. The predicted circuit-performance using Po-SiO was 10 % higher than that with porous SiOC. The electromigration reliability in 22 nm generation was consistent with the previous generations. The merit of EUV lithography on circuit design was also clarified.

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