Noise behavior of ferro electric tunnel FET

Abstract In this paper the noise behavior of ferroelectric TFET is explored for the first time. The effect of ferro-thickness, gate length, buffer type, and buffer thickness on current noise power spectral Density (SID) and voltage noise power spectral Density (SVG) along with electrical parameters such as memory window, subthreshold swing along with have been investigated. The normalized SID follows 1/SS2 trend, thus signifies the dominancy of BTBT over TAT in Ferro-TFET. Input referred noise PSD, SVG remains constant for whole range of gate voltage deviating from the nature for conventional MOSFET.Power spectral densities experience a sharp rise for frequency above 0.1 ​GHz due to dominancy of diffusion over other source of noise.

[1]  Chenming Hu,et al.  Green transistor as a solution to the IC power crisis , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[2]  S. Datta,et al.  Electrical Noise in Heterojunction Interband Tunnel FETs , 2014, IEEE Transactions on Electron Devices.

[3]  S. Datta,et al.  Can the subthreshold swing in a classical FET be lowered below 60 mV/decade? , 2008, 2008 IEEE International Electron Devices Meeting.

[4]  S. Datta,et al.  Use of negative capacitance to provide voltage amplification for low power nanoscale devices. , 2008, Nano letters.

[5]  S. Jit,et al.  A Novel Four-Terminal Ferroelectric Tunnel FET for Quasi-Ideal Switch , 2015, IEEE Transactions on Nanotechnology.

[6]  Brinda Bhowmick,et al.  Effect of scaling on noise in Circular Gate TFET and its application as a digital inverter , 2016, Microelectron. J..

[7]  Deepti Gola,et al.  Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors , 2017 .

[8]  Masaharu Kobayashi,et al.  Negative Capacitance for Boosting Tunnel FET performance , 2017, IEEE Transactions on Nanotechnology.

[9]  K. Boucart,et al.  The Hysteretic Ferroelectric Tunnel FET , 2010, IEEE Transactions on Electron Devices.

[10]  Adrian M. Ionescu,et al.  Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric , 2016 .

[11]  P. Singh,et al.  2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure , 2018, IEEE Transactions on Electron Devices.

[12]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[13]  P. Singh,et al.  2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure , 2017, IEEE Transactions on Electron Devices.

[14]  A. Ionescu,et al.  Non-hysteretic ferroelectric tunnel FET with improved conductance at Curie temperature , 2010, 68th Device Research Conference.

[15]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.