Design model for minority-carrier well-type guard-rings in CMOS circuits

A novel analytic model for minority-carrier well-type guard ring design has been developed for CMOS circuits. This model, expressed as a function of epi-layer thickness, well junction depth, and guard ring width, has been verified by two-dimensional numerical simulation as well as by experimental data. Also, the model has been confirmed to be valid by temperature measurements. The effect of a floating well-type guard ring has been addressed.<<ETX>>