Data path structures and heuristics for testable allocation in high level synthesis

Abstract This paper presents a new testable allocation scheme that has been included in a high level synthesis environment to enhance the testability of the circuits synthesized. Designs obtained have small area overheads and no delays in critical timing parts of the circuit thanks to the testable structure generated by the simultaneous optimization of testability and cost during the exploration of the design space. Some heuristics are introduced that reduce the search time with no space bounding.