Successful integration of IP/VC blocks requires a set of view that provides the appropriate information for each IP block through the design flow for an IP-integration system. In this paper, we present a methodology of IP integration in a System-on a chip (SOC) design, that exploits both IP designer and SOC integrator constraints. First, we describe a method to extract and specify IP functional and timing constraints (I/O sequence transfer constraints) from the IP core. Second, we propose a modeling style of the integration constraints and a technique for merging them with IP constraints. This technique allows the specification and design of an optimized IP interface unit required for IP-socketization. The synthesis output is synthesizable VHDL RT of the interface, a detailed bus-functional model of the IP core towards cosimulation.
[1]
Alberto L. Sangiovanni-Vincentelli,et al.
Interface-based design
,
1997,
DAC.
[2]
Daniel D. Gajski,et al.
High ― Level Synthesis: Introduction to Chip and System Design
,
1992
.
[3]
Jean Luc Philippe,et al.
A formal technique for hardware interface design
,
1998
.
[4]
Frank Vahid,et al.
Techniques for reducing read latency of core bus wrappers
,
2000,
DATE '00.
[5]
Alberto L. Sangiovanni-Vincentelli,et al.
Automatic synthesis of interfaces between incompatible protocols
,
1998,
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).