High-speed programmable FPGA Configuration through JTAG

Over the past few decades, the use of reconfigurable computing for aerospace applications has become increasingly common despite its sensitivity to ionizing radiation. Tools are needed to test and implement fault-mitigation mechanisms to increase the reliability of FPGAs in space. This paper introduces a tool called the JTAG Configuration Manager (JCM) that provides high-speed programmable access to the configuration memory of Xilinx FPGAs using the JTAG serial protocol. The JCM consists of a linux-based software library running on an embedded ARM processor paired with a hardware state machine implemented in programmable logic. Two important uses of the JCM are configuration scrubbing and fault injection. The high-speed JTAG interface allows such operations to run at up to 60 MHz, which is several times faster than traditional JTAG FPGA configuration methods. The JCM also has access to the XADC on-chip temperature monitoring and the internal Boundary SCAN, making it useful for many testing and debugging applications.

[1]  David Merodio Codinachs,et al.  In-flight reconfigurable FPGA-based space systems , 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[2]  Neeraj Suri,et al.  Sustaining Property Verification of Synchronous Dependable Protocols Over Implementation , 2007 .

[3]  Harald Michalik,et al.  Read back scrubbing for SRAM FPGAs in a data processing unit for space instruments , 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[4]  Aaron Gerald Stoddard Configuration Scrubbing Architectures for High-Reliability FPGA Systems , 2015 .

[5]  Zdenek Kotásek,et al.  SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems , 2011, 2011 14th Euromicro Conference on Digital System Design.

[6]  Gabriel L. Nazar,et al.  Fast single-FPGA fault injection platform , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[7]  Marcin Lukowiak,et al.  A new architecture for single-event detection & reconfiguration of SRAM-based FPGAs , 2007, 10th IEEE High Assurance Systems Engineering Symposium (HASE'07).

[8]  Heather M. Quinn,et al.  A Test Methodology for Determining Space Readiness of Xilinx SRAM-Based FPGA Devices and Designs , 2009, IEEE Transactions on Instrumentation and Measurement.

[9]  E. Kamanu,et al.  A new architecture for single-event detection & reconfiguration of SRAM-based FPGAs , 2007 .

[10]  Hassan Mostafa,et al.  Performance evaluation of dynamic partial reconfiguration techniques for software defined radio implementation on FPGA , 2015, 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).