Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking

This paper addresses the design and FPGA-prototyping of asynchronous circuits using static data-flow handshake components implemented using the two-phase bundled-data protocol. The contributions are partly tutorial and partly scientific. The paper introduces the design process, including initialization and design of coupled rings with any number of tokens. Following this, the paper presents gate-level implementations of the full set of handshake components as well as some peephole optimizations that merge the implementation of several components. The components are implemented using the click-template. The handshake register implementation is extended with circuitry that decouples the phase of the handshake signals on the input and output ports. Such decoupling is needed to facilitate implementation of rings with one token (or in the general case, rings with any number of tokens). Finally, the paper illustrates the design process using two circuits: one that outputs the sequence of Fibonacci numbers, and one that computes the greatest common divisor of two positive integers. All components are described in VHDL, and all code is available as open source. All components and the two circuits mentioned have been tested on a Xilinx Nexys4DDR FPGA board.

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