Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development

Abstract The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. The common goal is designing and implementing a physical rack prototype together with its cooling system, the non-volatile memory (NVM) architecture and a unified low-latency interconnect able to test different options for network and storage. Furthermore, the consortium goal is to provide real HPC applications to validate the system. In this paper we describe the unified data and storage network architecture, reporting on the status of development of different testbeds and highlighting preliminary benchmark results obtained through the execution of scientific, engineering and data analytics scalable application kernels.

[1]  Antonio Ragagnin,et al.  Galactic outflow and diffuse gas properties at z ≥ 1 using different baryonic feedback models , 2014, 1411.1409.

[2]  William J. Dally.  Virtual-channel flow control , 1990, ISCA '90.

[3]  Y. Zhang,et al.  The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems , 2016, 2016 Euromicro Conference on Digital System Design (DSD).

[4]  Davide Rossetti,et al.  APEnet+ 34 Gbps data transmission system and custom transmission logic , 2013 .

[5]  Klaus Dolag,et al.  Simulating realistic disk galaxies with a novel sub-resolution ISM model , 2014, 1411.3671.

[6]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[7]  Rainer Leupers,et al.  Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms , 2016, J. Syst. Archit..

[8]  Pier Stanislao Paolucci,et al.  The Next Generation of Exascale-Class Systems: The ExaNeSt Project , 2017, 2017 Euromicro Conference on Digital System Design (DSD).

[9]  Davide Rossetti,et al.  Architectural improvements and technological enhancements for the APEnet+ interconnect system , 2015, ArXiv.

[10]  Leonard Kleinrock,et al.  Virtual Cut-Through: A New Computer Communication Switching Technique , 1979, Comput. Networks.

[11]  V. Springel.  The Cosmological simulation code GADGET-2 , 2005, astro-ph/0505010.

[12]  Steve Plimpton,et al.  Fast parallel algorithms for short-range molecular dynamics , 1993 .

[13]  P. Monaco,et al.  The pinocchio algorithm: pinpointing orbit-crossing collapsed hierarchical objects in a linear density field , 2001 .

[14]  Javier Navaridas,et al.  Designing an exascale interconnect using multi-objective optimization , 2017, 2017 IEEE Congress on Evolutionary Computation (CEC).

[15]  Paul M. Carpenter,et al.  EUROSERVER: Share-anything scale-out micro-server design , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[16]  Martin L. Kersten,et al.  Database Architecture Evolution: Mammals Flourished long before Dinosaurs became Extinct , 2009, Proc. VLDB Endow..

[17]  Davide Rossetti,et al.  Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system , 2015 .

[18]  Javier Navaridas,et al.  High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings , 2018, ICS.