VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmetic

Computer simulations using SPICE establish the feasibility of implementing a highly pipelined high-speed FIR digital filter using Multiple-Valued Logic (MVL) Read-Only Memories (ROM's) to implement Residue Number System (RNS) Arithmetic in VLSI technology. A single VLSI chip can be used to convert from 8-bit binary to a 16-bit RNS with one additional chip to convert back. The basic approach proposed could be implemented in I^{2}L , MOS, CMOS, or ECL technologies. A detailed design and simulation using ECL technology yields less than 20 000 gates and less than 13-W power dissipation per filter weight. A maximum throughput rate of 30 MHz can be achieved with an ECL design based on partitioning the circuit into 2.5 VLSI chips.per filter weight. A MOS or CMOS design can yield a considerable power savings with a corresponding reduction in throughput rate and number of VLSI chips while an (Integrated Injection Logic) (I^{2} L) design can achieve moderate speed and moderate power consumption with relative/low power supply voltages.

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