Digitally Assisted Performance Tuning of Analog/RF Circuits with an On-Chip FFT Engine

A serious drawback associated with systems-on-a-chip integration and CMOS technology scaling trends is the increasing susceptibility to manufacturing process variations and aging effects. Consequently, it is critical to improve on-chip measurement and self-calibration capabilities as well as the testability of single-chip systems. This chapter describes a robust design methodology for enhanced reliability of analog front-end circuits in mixed-signal chips. The system under development is comprised of small blocks close to high-frequency analog circuits under test to down-convert signals to low frequencies such that they can be routed to an on-chip analog-to-digital converter architecture for built-in testing applications. An efficient Fast Fourier Transform (FFT) engine is used to calculate the frequency spectrum of the signal with significantly less chip area compared to existing FFT engines. The self-contained system provides the measurement results in digital form to support digital calibration approaches, particularly those that involve digitally assisted analog blocks. Marvin Onabajo Northeastern University, USA Yong-Bin Kim Northeastern University, USA Yongsuk Choi Northeastern University, USA Hari Chauhan Northeastern University, USA Chun-hsiang Chang Northeastern University, USA In-Seok Jung Northeastern University, USA DOI: 10.4018/978-1-4666-6627-6.ch010