Functional Test-Case Generation by a Control Transaction Graph for TLM Verification

Transaction level modeling allows exploring several SoC design architectures leading to better performance and easier verification of the final product. Test cases play an important role in determining the quality of a design. Inadequate test-cases may cause bugs to remain after verification. Although TLM expedites the verification of a hardware design, the problem of having high coverage test cases remains unsettled at this level of abstraction. In this paper, first, in order to generate test-cases for a TL model we present a Control-Transaction Graph (CTG) describing the behavior of a TL Model. A Control Graph is a control flow graph of a module in the design and Transactions represent the interactions such as synchronization between the modules. Second, we define dependent paths (DePaths) on the CTG as test-cases for a transaction level model. The generated DePaths can find some communication errors in simulation and detect unreachable statements concerning interactions. We also give coverage metrics for a TL model to measure the quality of the generated test-cases. Finally, we apply our method on the SystemC model of AMBA-AHB bus as a case study and generate test-cases based on the CTG of this model.

[1]  Ye Yi-zheng,et al.  The improvement for transaction level verification functional coverage , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[2]  Franco Fummi,et al.  On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[3]  Kshitiz Jain,et al.  Verification of transaction-level SystemC models using RTL testbenches , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..

[4]  Wolfgang Rosenstiel,et al.  SystemC: methodologies and applications , 2003 .

[5]  Fernando Gehm Moraes,et al.  From VHDL register transfer level to SystemC transaction level modeling: a comparative case study , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[6]  Sofiène Tahar,et al.  Efficient Assertion Based Verification using TLM , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[7]  Frank Ghenassia,et al.  Transaction Level Modeling with SystemC , 2005 .

[8]  Richard N. Taylor,et al.  Structural Testing of Concurrent Programs , 1992, IEEE Trans. Software Eng..

[9]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[10]  Sofiène Tahar,et al.  Enabling SystemC Verification using Abstract State Machines , 2004, FDL.

[11]  Sudeep Pasricha.  Transaction level modeling of SoC with SystemC 2.0 , 2004 .