Test-Pattern Generation Based on Reed-Muller Coefficients

Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits. The proposed pattern-generating procedure does not need a simulation of the circuit for each of the possible stuck-at faults, and its complexity is proportional to the number of gates in the circuit. The proportionality constant increases exponentially as the number of inputs in the circuit increases. To evaluate the performance of the proposed method, its application to some benchmark circuits, including the ALU 74181, is presented. >

[1]  Edward J. McCluskey,et al.  Design for autonomous test , 1981 .

[2]  Claudio Moraga,et al.  THE CHRESTENSON TRANSFORM IN PATTERN ANALYSIS , 1985 .

[3]  J J Hopfield,et al.  Neural networks and physical systems with emergent collective computational abilities. , 1982, Proceedings of the National Academy of Sciences of the United States of America.

[4]  Edward J. McCluskey,et al.  Pseudorandom Testing , 1987, IEEE Transactions on Computers.

[5]  Gary D. Hachtel,et al.  BEATNP: a tool for partitioning Boolean networks , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[6]  J. Ortega,et al.  The fast Tamari transform , 1991 .

[7]  Joseph L. A. Hughes.  Multiple fault detection using single fault test sets , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  M. G. Karpovsky,et al.  UNIVERSAL TESTING OF COMPUTER HARDWARE1 , 1985 .

[9]  Edward J. McCluskey,et al.  Test Length for Pseudorandom Testing , 1987, IEEE Transactions on Computers.

[10]  Hideo Fujiwara,et al.  The Complexity of Fault Detection Problems for Combinational Logic Circuits , 1982, IEEE Transactions on Computers.

[11]  J. Muzio,et al.  Spectral testing of circuit realisations based on linearisations , 1986 .

[12]  Bing J. Sheu,et al.  Hardware annealing in electronic neural networks , 1991 .

[13]  Edward J. McCluskey,et al.  Self-Testing Embedded Parity Checkers , 1984, IEEE Transactions on Computers.

[14]  Bing J. Sheu,et al.  Modified Hopfield neural networks for retrieving the optimal solution , 1991, IEEE Trans. Neural Networks.

[15]  Dhiraj K. Pradhan,et al.  Aliasing Probability for Multiple Input Signature Analyzer , 1990, IEEE Trans. Computers.

[16]  J.A. Abraham,et al.  Fault and error models for VLSI , 1986, Proceedings of the IEEE.

[17]  Hideo Fujiwara.  Computational Complexity of Controllability/Observability Problems for Combinational Circuits , 1990, IEEE Trans. Computers.

[18]  Sharad C. Seth,et al.  An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing , 1984, IEEE Trans. Computers.

[19]  Robert I. Damper,et al.  Physical faults in MOS circuits and their coverage by different fault models , 1988 .

[20]  Alberto Prieto,et al.  Using Reed-Muller coefficients to synthesise optimal prediction modules for concurrent testing , 1991 .

[21]  I. L. Sayers,et al.  Implementation of 32-bit RISC processor incorporating hardware concurrent error detection and correction , 1990 .

[22]  Edward J. McCluskey,et al.  Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs , 1984, IEEE Transactions on Computers.

[23]  Alfred K. Susskind,et al.  Testing by Verifying Walsh Coefficients , 1983, IEEE Transactions on Computers.

[24]  D.K. Pradhan,et al.  Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems , 1986, Proceedings of the IEEE.

[25]  George Markowsky,et al.  The Weighted Syndrome Sums Approach to VLSI Testing , 1981, IEEE Transactions on Computers.

[26]  J. Ortega,et al.  Universal built-in self-test procedure for CMOS PLA's , 1991 .

[27]  K. C. Y. Mei,et al.  Bridging and Stuck-At Faults , 1974, IEEE Transactions on Computers.

[28]  Mark G. Karpovsky,et al.  Fault Detection in Combinational Networks by Reed-Muller Transforms , 1989, IEEE Trans. Computers.

[29]  Edward McCluskey,et al.  Built-In Self-Test Structures , 1985, IEEE Design & Test of Computers.

[30]  D. Green.  Families of Reed-Muller canonical forms , 1991 .

[31]  Stanley L. Hurst.  The logical processing of digital signals , 1978 .

[32]  Edward J. McCluskey,et al.  Concurrent Error Detection and Testing for Large PLA's , 1982 .

[33]  J J Hopfield,et al.  Neurons with graded response have collective computational properties like those of two-state neurons. , 1984, Proceedings of the National Academy of Sciences of the United States of America.

[34]  Eiji Fujiwara,et al.  A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing , 1987, IEEE Transactions on Computers.

[35]  Edward J. McCluskey,et al.  Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets , 1986, ITC.

[36]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[37]  Sudhakar M. Reddy,et al.  On the Detection of Terminal Stuck-Faults , 1978, IEEE Transactions on Computers.

[38]  Jacob A. Abraham,et al.  Concurrent error detection in highly structured logic arrays , 1984 .

[39]  M. Karpovsky,et al.  Detection of stuck-at and bridging faults in Reed-Muller canonical (RMC) networks , 1989 .

[40]  C.R. Edwards.  The Application of the Rademacher–Walsh Transform to Boolean Function Classification and Threshold Logic Synthesis , 1975, IEEE Transactions on Computers.

[41]  F. Brglez,et al.  Circuit partitioning for logic synthesis , 1991 .

[42]  Israel Koren,et al.  On Switching Policies for Modular Redundancy Fault-Tolerant Computing Systems , 1987, IEEE Transactions on Computers.

[43]  S. M Reddy,et al.  Easily testable realizations for logic functions , 1973 .

[44]  Douglas M. Blough,et al.  Performance Analysis of a Generalized Concurrent Error Detection Procedure , 1990, IEEE Trans. Computers.

[45]  Kishor S. Trivedi,et al.  Coverage Modeling for Dependability Analysis of Fault-Tolerant Systems , 1989, IEEE Trans. Computers.

[46]  Gary S. Ditlow,et al.  Random Pattern Testability , 1984, IEEE Transactions on Computers.

[47]  Oscar H. Ibarra,et al.  Polynomially Complete Fault Detection Problems , 1975, IEEE Transactions on Computers.

[48]  Eiji Fujiwara,et al.  A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing , 1984, IEEE Transactions on Computers.

[49]  Yashwant K. Malaiya,et al.  The Coverage Problem for Random Testing , 1984, ITC.

[50]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[51]  S. A. Al-Arian,et al.  Physical failures and fault models of CMOS circuits , 1987 .

[52]  Bella Bose,et al.  PLA Implementation of k-out-of-n Code TSC Checker , 1984, IEEE Transactions on Computers.

[53]  Kang G. Shin,et al.  Error Detection Process - Model, Design, and Its Impact on Computer Performance , 1984, IEEE Trans. Computers.

[54]  D. Michael Miller,et al.  Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks , 1984, IEEE Transactions on Computers.

[55]  Francisco J. Pelayo,et al.  Optimization Problems on Concurrent Testing Solved by Neural Networks , 1991, IWANN.

[56]  Stanley L. Hurst,et al.  Spectral techniques in digital logic , 1985 .

[57]  Mark G. Karpovsky,et al.  Spectral Techniques and Fault Detection , 1985 .

[58]  Niraj K. Jha,et al.  Detecting Multiple Faults in CMOS Circuits , 1986, ITC.

[59]  Bella Bose,et al.  Theory of Unidirectional Error Correcting/Detecting Codes , 1978, IEEE Transactions on Computers.

[60]  D. Michael Miller,et al.  Spectral Fault Signatures for Internally Unate Combinational Networks , 1983, IEEE Transactions on Computers.

[61]  Prabhakar Goel.  Test generation costs analysis and projections , 1980, DAC '80.

[62]  Gintaras V. Reklaitis,et al.  Nonlinear Optimization Using Generalized Hopfield Networks , 1989, Neural Computation.

[63]  Kewal K. Saluja,et al.  A concurrent testing technique for digital circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[64]  Sudhakar M. Reddy,et al.  Fault Detecting Test Sets for Reed-Muller Canonic Networks , 1975, IEEE Transactions on Computers.

[65]  Javad Khakbaz,et al.  A Testable PLA Design with Low Overhead and High Fault Coverage , 1984, IEEE Transactions on Computers.