Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems

Standby power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× standby leakage reduction at VDD=4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.

[1]  Vivek De,et al.  A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[2]  S. Narendra,et al.  Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[3]  David Blaauw,et al.  A cubic-millimeter energy-autonomous wireless intraocular pressure monitor , 2011, 2011 IEEE International Solid-State Circuits Conference.

[4]  Vivek De,et al.  Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED '01.

[5]  S. Borkar,et al.  Dynamic-sleep transistor and body bias for active leakage power control of microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[6]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[7]  David Blaauw,et al.  A modular 1mm3 die-stacked sensing platform with optical communication and multi-modal energy harvesting , 2012, 2012 IEEE International Solid-State Circuits Conference.

[8]  Massimo Alioto,et al.  Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.