A new architecture of broadband network system suitable for asymmetric digital subscriber line application

This paper presents the design and implementation on a new architecture of broadband network system which suitable for asymmetric digital subscriber line (ADSL) application. The main design skill is based on the cell-based digital IC design process, and is implemented in 0.18 µm 1P6M CMOS process. The main function of this chip is to build a bridge between Ethernet and ATM which is used to substitute for RISC processor, leading to enhance the broadband network switching ability and stability. Furthermore, the clock management system is adopted to manage the packages. By this technique, a small size and low cost chip will be obtained.

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