Pipelining of high performance synchronous digital systems

A new approach is described to the design of those synchronous digital systems in which the performance parameters latency and clock frequency are of primary importance. Specifically, the trade-off between clock frequency and latency is analysed in terms of the circuit characteristics of a pipelined data path. A design paradigm relating latency and clock frequency as a function of the level of pipelining is described for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems from which the optimal level of pipelining can be determined in terms of the delays of logic, interconnect, and registers, and the clock skew and number of logic stages.