A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

Continuous-time delta-sigma modulators (CT-DSMs) are well suited for the baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. For example, 5 downlink component carriers are no longer sufficient to meet the ITU requirement for IMT-advanced and up to 32 carriers and 640MHz RF bandwidth are under discussion for 3GPP Release 13. This increased BW drives CT-DSMs to operate at a several-GHz clock rate, but comes at a cost of higher power consumption, even when utilizing advanced nanometer CMOS technologies. Previous >100MHz-BW CT-DSMs required a 4GHz clock rate with oversampling-ratio (OSR) beyond 13× and power exceeding 250mW [1,2]. By contrast, the proposed CT-DSM decreases the OSR to 9× while consuming 40mW to achieve 72dB DR within 160MHz BW.

[1]  Ping Chen,et al.  A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  José Silva-Martínez,et al.  A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[3]  Stacy Ho,et al.  A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[4]  Kofi A. A. Makinwa,et al.  A 4GHz CT ΔΣ ADC with 70dB DR and −74dBFS THD in 125MHz BW , 2011, 2011 IEEE International Solid-State Circuits Conference.

[5]  Stacy Ho,et al.  A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[6]  John G. Kauffman,et al.  An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization , 2011, 2011 IEEE International Solid-State Circuits Conference.

[7]  Hajime Shibata,et al.  A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW , 2012, 2012 IEEE International Solid-State Circuits Conference.

[8]  Shanthi Pavan,et al.  Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs , 2012, IEEE Journal of Solid-State Circuits.