Digitally programmable gain control circuit for charge-domain signal processing

A simple, nearly passive circuit for programmable gain control of charge-domain signals is described. The circuit is functionally equivalent to a multiplying digital-to-analog converter (MDAC) and is implemented in a 3- mu m double-poly, double-metal charge-coupled device (CCD) process. Two implementations of the circuit are reported: a single-stage recursive converter, and a ten-stage pipeline converter. The latter occupies 0.4 mm/sup 2/ of chip area and consumes approximately 2 mu W for a 1-kHz conversion rate. The circuit is shown experimentally to have all 8-b equivalent accuracy in both differential and integral linearity and is expected to find application in focal-plane image processing for both detector nonuniformity correction and convolution weighting. >

[1]  Eric R. Fossum.  Charge-Coupled Computing For Focal Plane Image Preprocessing , 1987 .

[2]  B. Coy,et al.  A 13000 gate 3 layer metal bipolar gate array , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[3]  Eric R. Fossum,et al.  Novel CCD Image Processor For Z-Plane Architecture , 1989, Defense, Security, and Sensing.

[4]  M. Yamamoto,et al.  Advanced ECL with new active pull-down emitter-followers , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[5]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[6]  J.D. Cressler,et al.  A submicrometer high-performance bipolar technology , 1989, IEEE Electron Device Letters.

[7]  S.S. Bencuya,et al.  Charge-packet splitting in charge-domain devices , 1984, IEEE Transactions on Electron Devices.

[8]  Daniel H. Sheingold,et al.  Analog-digital conversion handbook , 1972 .

[9]  M. Suzuki,et al.  A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocell , 1987 .