A flexible transform processor architecture for multi-CODECs (JPEG, MPEG-2, 4 and H.264)

This paper proposes a flexible architecture of the transform processor for multi-CODECs (JPEG, MPEG-2, 4 and H.264). Also the memory control scheme to efficiently store intermediate data is presented. In the proposed architecture, four arrays block process at the same time with 4 parallel process elements and pipelined structure for improving the processing time. For verification, FPGA platform with ARM-9 core is used. The results show that the proposed architecture satisfies the requirements of each CODECS such as JPEG, MPEG-2, 4 and H.264 standard

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