PLL-based BiCMOS on-chip clock generator for very high speed microprocessor

A phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is employed to generate an internal clock synchronized to a reference clock from outside a chip, has been developed using 1.0-μm BiCMOS technology. In order to obtain a very wide operation bandwidth, it is proposed that the PCG included a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the vibration bandwidth of the VCO according to the reference clock frequency, preventing the expected vibration frequency from being outside the vibration bandwidth. Therefore, the operation bandwidth of the PCG is from 3 MHz to 90 MHz. If semiconductor technology is enhanced, it should be possible to realize a clock generator operating near 200 MHz