Life is CMOS: why chase the life after?

This paper discusses potential solutions to the CMOS device technology scaling at gate lengths approaching 10nm. Promising circuit and design techniques to control leakage power are described. Energy-efficient microarchitecture trends for general-purpose microprocessors are elucidated.

[1]  G. Dewey,et al.  30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[2]  J. Kavalieros,et al.  A 50 nm depleted-substrate CMOS transistor (DST) , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[3]  Fred J. Pollack New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only) , 1999, MICRO.