The Design of High Resolution Time to Digit Converter Based on FPGA

The paper introduces a new design method of Time-to-Digital Converter with high precision, which invokes the PLL and Ring Shift Register in the chip. The circuit applying the design method has been implemented in FPGA/CPLD (Field Programmable Gate Array or Complex Programmable Logic Device) ,and it could be used as the functional circuit dependently or implanted into other SOC (System on Chip) designs conveniently. The precision with 3.3 nanoseconds can be achieved in Stratix and Cyclone series chip produced by Altera. Timing simulation and testing data indicate the method is right and feasible.