Introduction to the Cell multiprocessor

This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the disign concept, the architecture and programming models, and the implementation.

[1]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[2]  K. Kutaragi,et al.  A microprocessor with a 128 b CPU, 10 floating-point MACs, 4 floating-point dividers, and an MPEG2 decoder , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[3]  U. Ghoshal,et al.  Refrigeration technologies for sub-ambient temperature operation of computing systems , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[4]  Masaaki Oka,et al.  Vector Unit Architecture for Emotion Synthesis , 2000, IEEE Micro.

[5]  Pong-Fei Lu,et al.  Physical design of a fourth-generation POWER GHz microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[6]  Michael Gschwind,et al.  Optimizing pipelines for power and performance , 2002, MICRO.

[7]  G. Burbach,et al.  Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[8]  Balaram Sinharoy,et al.  Design and implementation of the POWER5 microprocessor , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  H. Iwai.  Future of CMOS technology , 2004, 2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846).

[10]  H. Peter Hofstee,et al.  Power efficient processor architecture and the cell processor , 2005, 11th International Symposium on High-Performance Computer Architecture.

[11]  S.H. Dhong,et al.  A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[12]  M. Horowitz,et al.  Clocking and circuit design for a parallel I/O on a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[13]  S. Asano,et al.  The design and implementation of a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..