Hyperspectral Compressive Sensing With a System-On-Chip FPGA

Advances in hyperspectral sensors have led to a significantly increased capability for high-quality data. This trend calls for the development of new techniques to enhance the way that such unprecedented volumes of data are stored, processed, and transmitted to the ground station. An important approach to deal with massive volumes of information is an emerging technique, called compressive sensing, which acquires directly the compressed signal instead of acquiring the full dataset. Thus, reducing the amount of data that needs to be measured, transmitted, and stored in first place. In this article, a hardware/software implementation in a system-on-chip (SoC) field-programmable gate array (FPGA) for compressive sensing is proposed. The proposed hardware/software architecture runs the compressive sensing algorithm with a unitary compression rate over an airborne visible/infrared imaging spectrometer sensor image with 512 lines, 614 samples, and 224 bands in 0.35 s. The proposed system runs <inline-formula><tex-math notation="LaTeX">$\text{49}\times$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$\text{216}\times$</tex-math></inline-formula> faster than an embedded 256-cores GPU of a Jetson TX2 board and the ARM of the SoC FPGA, respectively. In terms of energy, the proposed architecture requires around <inline-formula><tex-math notation="LaTeX">$\text{100} \times$</tex-math></inline-formula> less energy.