A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching Activity

Currents injected by CMOS digital circuit blocks into the powergrid and into the substrate of a system-on-a-chip may affect reliabilityand performance of other sensitive circuit blocks. To verify thecorrect operation of the system, an upper bound for the spectrum ofthe noise current has to be provided with respect to all possible transitionsof the circuit inputs. The number of input transitions is exponentialin the number of circuit inputs. In this paper, we present anovel approach for the computation of the upper bound that avoidsthe untractable exhaustive exploration of the entire space. Its computationalcomplexity is indeed linear in the number of gates. Ourapproach requires CMOS standard cell libraries to be characterizedfor injected noise current. In this paper, we also present an approachfor this characterization of CMOS standard cells. Experimental resultshave proven the accuracy of both the algorithm and the noisecurrent models used for the library characterization.

[1]  Shen Lin,et al.  Challenges in power-ground integrity , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[2]  Kurt Keutzer,et al.  Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Alper Demir,et al.  Modeling and simulation of the interference due to digital switching in mixed-signal ICs , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[4]  Karem A. Sakallah,et al.  Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time , 1996, DAC '96.

[5]  Kwang-Ting Cheng,et al.  Vector generation for maximum instantaneous current through supply lines for CMOS circuits , 1997, DAC.

[6]  Ibrahim N. Hajj,et al.  Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1998, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[8]  S. Chowdhury,et al.  Estimation of maximum currents in MOS IC logic circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Ibrahim N. Hajj,et al.  Estimation of maximum current envelope for power bus analysis and design , 1998, ISPD '98.

[10]  Alberto Sangiovanni-Vincentelli,et al.  Substrate noise: analysis and optimization for IC design [Book Review] , 2002, IEEE Circuits and Devices Magazine.