IEEE C37.118.1a-2014 Compliance Testing of EPLL and DFAC-PLL for Synchrophasors

Phase Locked Loop (PLL) methods are mainly used for frequency tracking and phase locking mechanism. Very few of the PLL methods are suggested in the literature for synchrophasor applications as they require estimation of amplitude along with the phase and frequency. In this paper compliance testing according to IEEE standard C37.118.1a-2014 is carried out for two PLL methods amenable for synchrophasor applications, namely enhanced PLL (EPLL) and double frequency & amplitude compensation PLL (DFAC-PLL).