Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology

This paper addresses a design and performance evaluation of ultra low-voltage non-clocked voltage comparator. The circuit was designed in a standard twin-well 130 nm CMOS technology and is intended to work in temperature range of -20 – 85 °C with the power supply voltage of 0.6 V. The proposed comparator can handle the input voltage within the rail-to-rail range. Low-voltage design approaches, namely, g m /I D design methodology in combination with the bulk-driven operation approach have been employed. The measurements on fabricated prototype chips included evaluation of both static as well as dynamic parameters. An excellent correlation between simulations and the measured bench data was observed. The proposed comparator is currently being reviewed and re-designed for even lower power supply voltage of 0.4 V.

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