A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture
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M. Wordeman | T. Kirihata | D. Netis | O. Weinfurtner | L. Hsu | J. Schnell | G. Mueller | M. Clinton | S. Loeffler | B. Ji | H. Terletzki | D. Hanson | Chorng-Lil Hwang | G. Lehmann | D. Storaska | G. Daniel | T. Boehler | G. Frankowsky | J. Ross | A. Reith | O. Kiehl
[1] J. Benzreba,et al. A 800 MB/s 72 Mb SLDRAM with digitally-calibrated DLL , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).