Robust FinFET Schmitt Trigger Designs for Low Power Applications

The IoT development alongside with the more pronounced impact of process variability in modern technology nodes, is the central reason to control variability impact. Given the broad set of IoT devices running on battery-oriented environments, energy consumption should be minimal and the operation reliable. Schmitt Trigger inverters are frequently used for noise immunity enhancement, and have been recently applied to mitigate radiation effects and variability impact. Yet, Schmitt Trigger operation at nominal voltage still introduces high deviation on power consumption. Thus, the main contribution of this work is to identify the relationship between transistor sizing, supply voltage, energy, and process variability robustness to achieve a minimal energy consumption circuit while keeping robustness. On average, scenarios with a lower supply voltage applied on layouts with a smaller number of fins, presented adequate robustness in high variability scenarios. Exploring voltage and transistor sizing made possible a reduction of about 24.84% on power consumption.

[1]  Cristina Meinhardt,et al.  Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations , 2014, Microelectron. Reliab..

[2]  Niraj K. Jha,et al.  FinFETs: From Devices to Architectures , 2014 .

[3]  Gracieli Posser,et al.  FinFET cells with different transistor sizing techniques against PVT variations , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[4]  Cristina Meinhardt,et al.  Evaluation of variability using Schmitt trigger on full adders layout , 2018, Microelectron. Reliab..

[5]  Said F. Al-Sarawi,et al.  Low power Schmitt trigger circuit , 2002 .

[6]  Martin M. Frank,et al.  Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges , 2006, IBM J. Res. Dev..

[7]  Ricardo Reis,et al.  Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[8]  Andrew R. Brown,et al.  Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study , 2010, IEEE Electron Device Letters.

[9]  Diederik Verkest,et al.  Standard cell design in N7: EUV vs. immersion , 2015, Advanced Lithography.

[10]  Aminul Islam,et al.  Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells , 2015, IET Circuits Devices Syst..

[11]  Duane S. Boning,et al.  Analysis and decomposition of spatial variation in integrated circuit processes and devices , 1997 .

[12]  Carlos Galup-Montoro,et al.  Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Asen Asenov.  RANDOM DOPANT INDUCED THRESHOLD VOLTAGE LOWERING AND FLUCTUATIONS IN SUB 50 NM MOSFETS: A STATISTICAL 3D 'ATOMISTIC' SIMULATION STUDY , 1999 .

[14]  Yiannos Manoli,et al.  Energy harvesting — from devices to systems , 2010, 2010 Proceedings of ESSCIRC.

[15]  Kaustav Banerjee,et al.  Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design , 2008, ICCAD 2008.

[16]  M. Mustafa,et al.  Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology , 2013 .

[17]  Massimo Alioto,et al.  Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  Yiannos Manoli,et al.  Ultra-Sub-Threshold Operation of Always-On Digital Circuits for IoT Applications by Use of Schmitt Trigger Gates , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Cristina Meinhardt,et al.  Investigating PVT variability effects on full adders , 2016, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[20]  Samar K. Saha,et al.  Modeling Process Variability in Scaled CMOS Technology , 2010, IEEE Design & Test of Computers.

[21]  Saurabh Sinha,et al.  ASAP7: A 7-nm finFET predictive process design kit , 2016, Microelectron. J..

[22]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[23]  Timothy A. Brunner,et al.  Why optical lithography will live forever , 2003 .

[24]  Chi Zhang,et al.  Low voltage CMOS Schmitt trigger circuits , 2003 .

[25]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[26]  Michel Steyaert,et al.  Novel cmos schmitt trigger , 1986 .

[27]  Bo Yang,et al.  Statistical prediction of circuit aging under process variations , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[28]  Aminul Islam,et al.  Circuit-Level Technique to Design Variation- and Noise-Aware Reliable Dynamic Logic Gates , 2018, IEEE Transactions on Device and Materials Reliability.

[29]  V. A. Pedroni,et al.  Low-voltage high-speed Schmitt trigger and compact window comparator , 2005 .

[30]  Massimo Alioto,et al.  Delay Variability Due to Supply Variations in Transmission-Gate Full Adders , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[31]  Mauro Olivieri,et al.  Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell , 2015, 2015 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions).

[32]  Wonchan Kim,et al.  A new waveform-reshaping circuit: an alternative approach to Schmitt trigger , 1993 .

[33]  Chih-Hong Hwang,et al.  Statistical variability in FinFET devices with intrinsic parameter fluctuations , 2010, Microelectron. Reliab..

[34]  S. Datta,et al.  High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack , 2003, IEEE International Electron Devices Meeting 2003.

[35]  Yung-Huei Lee,et al.  Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability , 2018, Microelectron. Reliab..

[36]  A. Pfister,et al.  Novel CMOS Schmitt trigger with controllable hysteresis , 1992 .

[37]  Cristina Meinhardt,et al.  Impact of gate workfunction fluctuation on FinFET standard cells , 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[38]  Z. Wang,et al.  CMOS adjustable Schmitt triggers , 1991 .

[39]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[40]  A. Asenov.  Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[41]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[42]  L. B. Moraes,et al.  Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability , 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

[43]  D. Frank,et al.  Simulation of stochastic doping effects in Si MOSFETs , 2000, 7th International Workshop on Computational Electronics. Book of Abstracts. IWCE (Cat. No.00EX427).

[44]  Farshad Moradi,et al.  Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective , 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

[45]  J. Stathis,et al.  Dielectric breakdown mechanisms in gate oxides , 2005 .

[46]  Yiannos Manoli,et al.  A 62 mV 0.13 $\mu$ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic , 2011, IEEE Journal of Solid-State Circuits.

[47]  S.R. Nassif.  Within-chip variability analysis , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[48]  M. L. Lovejoy,et al.  Fermi-level pinning at the polysilicon/metal-oxide interface-Part II , 2004, IEEE Transactions on Electron Devices.

[49]  S. Dasgupta,et al.  Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS , 2010, IEEE Transactions on Electron Devices.

[50]  Aristos Christou,et al.  Failure mechanism models for electromigration , 1994 .

[51]  Sani R. Nassif,et al.  Process variability at the 65nm node and beyond , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[52]  E. Takeda,et al.  An empirical model for device degradation due to hot-carrier injection , 1983, IEEE Electron Device Letters.

[53]  Tsu-Jae King,et al.  FinFETs for nanoscale CMOS digital integrated circuits , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[54]  Fabrizio Lombardi,et al.  Modeling Open Defects in Nanometric Scale CMOS , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

[55]  Imrich Chlamtac,et al.  Internet of things: Vision, applications and research challenges , 2012, Ad Hoc Networks.

[56]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.