Convertibility verification and converter synthesis: two faces of the same coin [IP block interfaces]

An essential problem in component-based design is how to compose components designed in isolation. Several approaches have been proposed for speeding component interfaces that capture behavioral aspects such as interaction protocols, and for verifying interface compatibility. Likewise, several approaches have been developed for synthesizing converters between incompatible protocols. In this paper, we introduce the notion of adaptability as the property that two interfaces have when they can be made compatible by communicating through a converter that meets specified requirements. We show that verifying adaptability and synthesizing an appropriate converter are two faces of the same coin: adaptability can be formalized and solved using a game-theoretic framework and then the converter can be synthesized as a strategy that always wins the game. Finally we show that this framework can be related to the rectification problem in trace theory.

[1]  Giovanni De Micheli,et al.  Modeling hierarchical combinational circuits , 1993, ICCAD.

[2]  Sagar Chaki,et al.  Types as models: model checking message-passing programs , 2002, POPL '02.

[3]  E. Emerson,et al.  Tree Automata, Mu-Calculus and Determinacy (Extended Abstract) , 1991, FOCS 1991.

[4]  Thomas A. Henzinger,et al.  Interface Theories for Component-Based Design , 2001, EMSOFT.

[5]  Alberto L. Sangiovanni-Vincentelli,et al.  Automatic synthesis of interfaces between incompatible protocols , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[6]  Alan J. Hu,et al.  Monitor-Based Formal Specification of PCI , 2000, FMCAD.

[7]  J. R. Büchi,et al.  Solving sequential conditions by finite-state strategies , 1969 .

[8]  Wolfgang Thomas,et al.  On the Synthesis of Strategies in Infinite Games , 1995, STACS.

[9]  Luciano Lavagno,et al.  Formal Models for Communication-Based Design , 2000, CONCUR.

[10]  Nancy A. Lynch,et al.  Hierarchical correctness proofs for distributed algorithms , 1987, PODC '87.

[11]  David L. Dill,et al.  Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.

[12]  Luciano Lavagno,et al.  Concurrent execution semantics and sequential simulation algorithms for the Metropolis meta-model , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[13]  Yuri Gurevich,et al.  Trees, automata, and games , 1982, STOC '82.

[14]  G. De Micheli,et al.  Modeling hierarchical combinational circuits , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[15]  Thomas A. Henzinger,et al.  Interface automata , 2001, ESEC/FSE-9.