Associative Memories and Processors: The Exact Match Paradigm

Associative or content addressable memories (CAM) are crucial in the implementation of high performance computing architectures for applications that require intensive data management or are cognitive in nature. The basic architecture of associative memories can be based on either the exact match or neural network models. This paper focuses on exact match associative memories. The milestone achievements in the field since the first associative memory implementation four decades ago are discussed. A classification of the diverse associative computing architectures is presented. It comprises of two levels of distinction, the associative memory organization and the processing capability which heavily depends on the application domain. Recent development in associative processing applications are also discussed which include fast routing in communication networks, memory management, database management, image processing, and artificial intelligence applications.

[1]  Kenneth J. Thurber,et al.  Associative and Parallel Processors , 1975, CSUR.

[2]  Azriel Rosenfeld,et al.  The DARPA Image Understanding Benchmark for Parallel Computers , 1990, J. Parallel Distributed Comput..

[3]  Erik L. Dagless,et al.  Design of an associative processor array , 1989 .

[4]  Lawrence Chisvin,et al.  Content-addressable and associative memory: alternatives to the ubiquitous RAM , 1989, Computer.

[5]  L. G. Johnson,et al.  Associative memory integrated circuit based on neural mutual inhibition , 1992 .

[6]  M. A. Wesley,et al.  A design for an auxiliary associative parallel processor , 1972, AFIPS '72 (Fall, part I).

[7]  M. A. Lucente,et al.  Memory system reliability improvement through associative cache redundancy , 1991 .

[8]  Y. Nakagome,et al.  An on-chip smart memory for a data-flow CPU , 1990 .

[9]  John V. Oldfield,et al.  Content-addressable memories applied to execution of logic programs , 1989 .

[10]  Hiroaki Terada,et al.  A 100-mega-access per second matching memory for a data-driven microprocessor , 1990 .

[11]  Masanori Hariyama,et al.  Design of a CAM-Based Collision Detection VLSI Processor for Robotics (Special Issue on Super Chip for Intelligent Integrated Systems) , 1994 .

[12]  Erik L. Dagless,et al.  A Survey on Trust Management for Mobile Ad Hoc Networks , 2011, IEEE Communications Surveys & Tutorials.

[13]  Ali R. Hurson,et al.  Parallel Architectures for Database Systems , 1989, Adv. Comput..

[14]  Chen-Yi Lee,et al.  High-speed median filter designs using shiftable content-addressable memory , 1994, IEEE Trans. Circuits Syst. Video Technol..

[15]  A. G. Hanlon Content-Addressable and Associative Memory Systems a Survey , 1966, IEEE Trans. Electron. Comput..

[16]  Dik Lun Lee,et al.  HYTREM - A Hybrid Text-Retrieval Machine for Large Databases , 1990, IEEE Trans. Computers.

[17]  Y. Murata,et al.  Real-time string search engine LSI for 800-Mbit/sec LANs , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[18]  Chen-Yi Lee,et al.  High-throughput data compressor designs using content addressable memory , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[19]  Hiroaki Kitano,et al.  The IXM2 parallel associative processor for AI , 1994, Computer.

[20]  José G. Delgado-Frias,et al.  VLSI for Artificial Intelligence , 1989 .

[21]  Jack A. Rudolph A production implementation of an associative array processor: STARAN , 1972, AFIPS '72 (Fall, part I).

[22]  M. Horowitz,et al.  A 4 ns BiCMOS translation-lookaside buffer , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[23]  J. V. Oldfield Logic programs and an experimental architecture for their execution , 1986 .

[24]  M. Bickley,et al.  The use of content addressable memories in the level 2 trigger for the CLAS detector at CEBAF , 1996, IEEE Transactions on Nuclear Science.

[25]  Albert Kaplan A Search Memory Subsystem for a General Purpose Computer , 1899 .

[26]  Ian N. Robinson Pattern-addressable memory , 1992, IEEE Micro.

[27]  Charles C. Weems Architectural requirements of image understanding with respect to parallel processing , 1991 .

[28]  Charles Sodini,et al.  A dynamic associative processor for machine vision applications , 1992, IEEE Micro.

[29]  B. T. McKeever The associative memory structure , 1965, AFIPS '65 (Fall, part I).

[30]  Erik L. Dagless,et al.  An associative processor array for image processing , 1989, Image Vis. Comput..

[31]  R. M. Lea,et al.  A 9-kbit associative memory for high-speed parallel processing applications , 1988 .

[32]  S. Jones,et al.  100 Mbit/s adaptive data compressor design using selectively shiftable content-addressable memory , 1992 .

[33]  R. M. Lea,et al.  ASP: a cost-effective parallel microcomputer , 1988, IEEE Micro.

[34]  Karl-Erwin Großpietsch,et al.  The associative processor system CAPRA: architecture and applications , 1992, IEEE Micro.

[35]  H. Bergh,et al.  A fault-tolerant associative memory with high-speed operation , 1990 .

[36]  R. Igarashi,et al.  A 150-nanosecond associative memory using integrated MOS transistors , 1966 .

[37]  J. Miyake,et al.  An 8-kbit content-addressable and reentrant memory , 1985, IEEE Journal of Solid-State Circuits.

[38]  C. Y. Lee Intercommunicating cells, basis for a distributed logic computer , 1962, AFIPS '62 (Fall).

[39]  Randy H. Katz,et al.  Disk system architectures for high performance computing , 1989, Proc. IEEE.

[40]  Edward W. Davis Application of the massively parallel processor to database management systems , 1983, AFIPS '83.

[41]  Ali R. Hurson,et al.  Parallel architectures for databases systems , 1989 .

[42]  Chie Dou,et al.  An efficient pattern match architecture for production systems using content-addressable memory , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[43]  Behrooz Parhami,et al.  Associative memories and processors: An overview and selected bibliography , 1973 .

[44]  A. J. McAuley,et al.  A self-testing reconfigurable CAM , 1991 .

[45]  A. Krikelis,et al.  Associative processing and processors , 1994, Computer.

[46]  John V. Oldfield,et al.  A general-purpose CMOS associative processor IC and system , 1992, IEEE Micro.

[47]  H.-C. Zeidler Content-addressable mass memories , 1989 .

[48]  H. Nagai,et al.  A high-speed string-search engine , 1987 .

[49]  Daniel L. Slotnick Logic per Track Devices , 1970, Adv. Comput..

[50]  Joseph L. Mundy,et al.  Low-cost associative memory , 1972 .

[51]  A. Cantoni,et al.  Cascading content-addressable memories , 1992, IEEE Micro.

[52]  R. H. Fuller,et al.  An associative parallel processor with application to picture processing , 1965, AFIPS '65 (Fall, part I).

[53]  Nikola K. Kasabov,et al.  Model for exploiting associative matching in AI production systems , 1995, Knowl. Based Syst..

[54]  T. Hanyu,et al.  2-transistor-cell 4-valued universal-literal CAM for a cellular logic image processor , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[55]  Paul Francis,et al.  Fast routing table lookup using CAMs , 1993, IEEE INFOCOM '93 The Conference on Computer Communications, Proceedings.

[56]  Anargyros Krikelis Computer Vision Applications with the Associative String Processor , 1991, J. Parallel Distributed Comput..

[57]  N. Correa,et al.  An ASIC CAM design for associative set processors , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[58]  Michel Dana,et al.  High-performance CAM-based Prolog execution scheme , 1991, Defense, Security, and Sensing.

[59]  Vannevar Bush,et al.  As we may think , 1945, INTR.

[60]  A. K. Goksel,et al.  A content addressable memory management unit with on-chip data cache , 1989 .

[61]  Djamshid Tavangarian Flag-oriented parallel associative architectures and applications , 1994, Computer.

[62]  Takashi Kimura,et al.  High-Speed CAM-Based Architecture for a Prolog Machine (ASCA) , 1988, IEEE Trans. Computers.

[63]  Behrooz Parhami Performance analysis and optimization of search and selection algorithms for highly parallel associative memories , 1996, Proceedings of MASCOTS '96 - 4th International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.

[64]  M. Hirata,et al.  A versatile data string-search VLSI , 1988 .

[65]  Adin D. Falkoff Algorithms for Parallel-Search Memories , 1962, JACM.

[66]  W. C. Meilander,et al.  Array processor supercomputers , 1989, Proc. IEEE.

[67]  P. Bruce Berra,et al.  The Role of Associative Array Processers in Data Base Machine Architecture , 1979, Computer.

[68]  Margaret H. Dunham,et al.  Join processing in relational databases , 1992, CSUR.

[69]  G. Jack Lipovski,et al.  A four megabit Dynamic Systolic Associative Memory chip , 1992, J. VLSI Signal Process..

[70]  L. G. Johnson,et al.  Associative IC memories with relational search and nearest-match capabilities , 1992 .

[71]  T. Ogura,et al.  A 20 kbit associative memory LSI for artificial intelligence machines , 1989 .

[72]  K. Hirata,et al.  A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM , 1990 .

[73]  P. Faudemay,et al.  An associative accelerator for large databases , 1991, IEEE Micro.

[74]  A. Baker,et al.  Content addressable memory for flash redundancy , 1991, [1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings.

[75]  Kirk Twardowski,et al.  An associative architecture for genetic algorithm-based machine learning , 1994, Computer.

[76]  Chong-Cheng Fu,et al.  Content-addressable memory for VLSI pattern inspection , 1988 .

[77]  Sargur N. Srihari,et al.  A special-purpose content addressable memory chip for real-time image processing , 1992 .

[78]  Tavangarian Flag-algebra: a new concept for the realisation of fully parallel associative architectures , 1989 .

[79]  A. E. Slade,et al.  A cryotron catalog memory system , 1956, AIEE-IRE '56 (Eastern).

[80]  R. M. Lea,et al.  Associative massively parallel computers , 1991, Proc. IEEE.

[81]  Sethuraman Panchanathan,et al.  A content-addressable memory architecture for image coding using vector quantization , 1991, IEEE Trans. Signal Process..

[82]  Paul M. Davies,et al.  An associative processor , 1964, AFIPS '64 (Fall, part I).

[83]  Subash Shankar A Hierarchical Associative Memory Architecture for Logic Programming Unification , 1988, ICLP/SLP.

[84]  H. Yamada,et al.  A string search processor LSI , 1990 .

[85]  C. G. Sodini,et al.  A ternary content addressable search engine , 1989 .

[86]  R. M. Lea SCAPE: a single-chip array processing element for signal and image processing , 1986 .

[87]  Stephen S. Yau,et al.  Associative Processor Architecture—a Survey , 1977, CSUR.

[88]  J. Minker An overview of associative or content addressable memory systems and a KWIC index to the literature , 1971 .

[89]  Kenneth E. Batcher,et al.  Bit-Serial Parallel Processing Systems , 1982, IEEE Transactions on Computers.

[90]  Ridha Djemal,et al.  Toward reconfigurable associative architecture for high speed communication operators , 1996, Proceedings IEEE Symposium and Workshop on Engineering of Computer-Based Systems.