eSRAM Reliability: Why is it still not optimally solved?

As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory’s individual components contribute to the memory’s overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.

[1]  Francky Catthoor,et al.  Mitigation of sense amplifier degradation using input switching , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[2]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[3]  Michael Nicolaidis,et al.  Reliability challenges of real-time systems in forthcoming technology nodes , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Francky Catthoor,et al.  Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Xiaofei Wang,et al.  SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data , 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

[6]  Francky Catthoor,et al.  Methodology for Application-Dependent Degradation Analysis of Memory Timing , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[7]  Sarita V. Adve,et al.  The impact of technology scaling on lifetime reliability , 2004, International Conference on Dependable Systems and Networks, 2004.

[8]  B. Parvais,et al.  Defect-based compact modeling for RTN and BTI variability , 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

[9]  Francky Catthoor,et al.  Bias Temperature Instability analysis of FinFET based SRAM cells , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  Wei Wu,et al.  A fast and provably bounded failure analysis of memory circuits in high dimensions , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[11]  Hamid Mahmoodi,et al.  Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[12]  S. Nassif,et al.  Analytical Modeling of SRAM Dynamic Stability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[13]  Yervant Zorian,et al.  Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.

[14]  Said Hamdioui,et al.  Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[16]  Ilia Polian,et al.  Analyzing the effects of peripheral circuit aging of embedded SRAM architectures , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[17]  A. Carlson.  Mechanism of Increase in SRAM $V_{\min}$ Due to Negative-Bias Temperature Instability , 2007, IEEE Transactions on Device and Materials Reliability.

[18]  Rob A. Rutenbar,et al.  Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Francky Catthoor,et al.  Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity , 2013, 2013 8th IEEE Design and Test Symposium.

[20]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[21]  Yu Cao,et al.  Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[22]  Francky Catthoor,et al.  Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[23]  Rob A. Rutenbar,et al.  Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[24]  Sani R. Nassif,et al.  Statistical analysis of SRAM cell stability , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[25]  N. Horiguchi,et al.  Response of a single trap to AC negative Bias Temperature stress , 2011, 2011 International Reliability Physics Symposium.

[26]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[27]  Ching-Te Chuang,et al.  Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability , 2009, Microelectron. Reliab..