Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System

In this paper, we apply the voltage overscaling (VOS) technique to the residue-number-system (RNS)-based digital signal processing system for achieving high energy efficiency. To mitigate the soft errors caused by VOS, we propose a new method, called joint RNS-RPR (JRR), which is the combination of RNS and the reduced precision redundancy (RPR) technique. The JRR technology inherits the properties of RNS, including shorter critical path, low complexity, and low power. Moreover, JRR can achieve higher power reduction than RNS for VOS applications. Since the soft errors caused by VOS lead to significant performance degradation of RNS, we use the information from RNS and RPR to achieve a high recovering probability of the soft errors with low hardware complexity. From the case study of finite impulse response (FIR) filter design based on the 0.25- μm 2.5-V CMOS technology, we find that JRR can save 62% more energy compared to the traditional FIR with a less than 2-dB signal noise ratio performance loss. We also find that JRR has lower complexity and better performance than the traditional soft error mitigation methods.

[1]  Naresh R. Shanbhag,et al.  Soft digital signal processing , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Anantha Chandrakasan,et al.  Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[3]  P. V. Ananda Mohan,et al.  RNS-to-Binary Converters for Two Four-Moduli Sets $\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}-1\}$ and $\{2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}+1\}$ , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Naresh R. Shanbhag,et al.  Low-power FFT via reduced precision redundancy , 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

[5]  Gerald E. Sobelman,et al.  Low-Power Bus Transform Coding for Multilevel Signals , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[6]  Mohammad Umar Siddiqi,et al.  Multiple error detection and correction based on redundant residue number systems , 2008, IEEE Transactions on Communications.

[7]  Houman Zarrabi,et al.  An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[8]  Gian Carlo Cardarilli,et al.  Low-power adaptive filter based on RNS components , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[9]  Hao Chen,et al.  Stochastic computational models for accurate reliability evaluation of logic circuits , 2010, GLSVLSI '10.

[10]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Naresh R. Shanbhag,et al.  Error-Resilient Low-Power Viterbi Decoder Architectures , 2009, IEEE Transactions on Signal Processing.

[12]  Naresh R. Shanbhag,et al.  Low-power filtering via adaptive error-cancellation , 2003, IEEE Trans. Signal Process..

[13]  A. T. Harding,et al.  Probability and statistics for engineers , 1969 .

[14]  Stanislaw J. Piestrak.  Design of multi-residue generators using shared logic , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[15]  Naresh R. Shanbhag,et al.  Reliable low-power digital signal processing via reduced precision redundancy , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  A. Premkumar,et al.  Comments on "Breaking the 2n-bit carry-propagation barrier in residue to binary conversion for the [2/sup n/-1, 2/sup n/, 2/sup n/+1] moduli set" and author's reply , 2001 .

[17]  H. Krishna,et al.  A coding theory approach to error control in redundant residue number systems. I. Theory and single error correction , 1992 .

[18]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[19]  Wayne H. Wolf,et al.  Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Nam Ik Cho,et al.  Low-Power Filtering Via Minimum Power Soft Error Cancellation , 2007, IEEE Transactions on Signal Processing.

[21]  Vassilis Paliouras,et al.  RNS multi-voltage low-power multiply-add unit , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[22]  Yvon Savaria,et al.  Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI , 1999 .

[23]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.