LOW PHASE NOISE DESIGN TECHNIQUES FOR PHASE LOCKED LOOP BASED INTEGRATED RF FREQUENCY SYNTHESIZERS

The explosive growth of wireless communication market today has brought an increasing demand for high performance radio-frequency integrated circuits (RFIC) at low cost. As a result, there is a great interest in integrating the various blocks of a communication system on a single chip transceiver. One of the most difficult components to integrate is the frequency synthesizer that generates the local oscillator (LO) carrier signal. The difficulty comes mostly from the very stringent phase noise performance requirements of the wireless application. In this dissertation, we are interested in improving phase noise performance of integrated phase-locked-loop (PLL) based radio-frequency (RF) frequency synthesizers. The most important phase noise contributors in a PLL are voltage controlled oscillator (VCO) and Phase Frequency Detector/Charge Pump/Frequency Dividers (PFD/CP/Divider). In this dissertation, we focus on the analysis of the phase noise generation mechanism in these key building blocks and the derivation of the analytical relationship between their phase noise performance and circuit design parameters. For VCO, based on the understanding of phase noise generation process in cross-coupled CMOS LC VCO, a simple yet accurate analytical phase noise model was proposed and a closed form formula for the fitting factor in Leeson's model is derived. For PFD/CP/Divider, due to the presence of many digital components, their phase noise model is studied from the point of view of timing jitter. The analytic equation that relates the PFD/CP/Divider 1Hz normalized phase noise floor and circuit parameters is derived. Based on the theoretical analysis, the design schemes for optimizing the phase noise performance are proposed and verified by simulation and experimental prototype measurement.

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