Overview of status and challenges of system testing on chip with embedded DRAMS

Abstract The combination of logic together with DRAM as a system on chip (SOC) has many advantages for a large variety of computing and network applications. The goal of testing a system is to detect the fabrication caused faults in order to guarantee the defined quality. The increasing size of memories, shrinking dimensions, higher demands on application (frequency and temperature range) and quality cause new problems and higher costs of testing. On the other hand the pressure to serve the market with low cost products forces the test engineer to reduce test costs by reducing test times and using low cost test equipment. Different solutions are discussed in this paper in order to meet these challenges. The variety of test approaches for testing SOC with embedded DRAMs reaches from testing with completely chip external test logic, a simple on-chip test logic up to a full blown built-in self test (BIST) on chip. Which choice is the right one depends on different criteria e.g. memory size, quality demands and application of the product. As an example the modular embedded DRAM core concept from Infineon Technologies is discussed, which includes a dedicated modular test concept based on on-chip integration of a test controller.

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