The design and performance of a miniaturized reverse modulation loop (RML) for a 120 Mbit/s coherent quadrature phase shift keying (CQPSK) modem for onboard satellite applications are presented. Analysis of time delays within the RML circuit indicates that any differential time-delay errors can adversely affect the associated BER and should be minimized. The RML circuit, consisting of a modulator, demodulator, and comparator circuit, has been fabricated using quasi-monolithic techniques with dimensions of 1.65*4 cm. The relative phase for all four states of the modulator is in close agreement with design values of 90 degrees +or-1 degrees over a 200 MHz bandwidth at 3.95 GHz. The demodulator and comparator circuits of the RML have successfully recovered a 120 Mbit/s bit stream. The RML circuit is capable of recovering higher bit rates because of relatively uniform amplitude and phase performance over the 3.7- to 4.2 GHz communications satellite band. >
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