On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation

The paper proposes an integrated methodology to abstract already existing heterogeneous IPs into SysML behavioral equivalent models. This approach aims at integrating the abstracted components with partially specified platforms at SysML level and verifying their integration. During the abstraction flow, the level of details can be chosen according to the needs of the designer. They are related to communication and synchronization protocols, hierarchical structure, and data types of the abstracted IPs and the details about continuous flows to be abstracted in SysML. Therefore, the generated SysML models can preserve information about structure in combination with the functional description for continuous and discrete behaviors and, thus, they can be synthesized into C++ or modeling tools like Matlab Simulink. This can be used to verify the integration of the so generated models exploiting simulation based techniques. The main benefit of the proposed methodology is relieving designers from the modeling time and error risks especially for those designs in which the SysML model of the architecture is particularly structured and detailed. The approach has been fully integrated and extended to support also components with analogic behaviors. The proposed framework has been applied positively to different benchmarks in order to be validated. Three case studies are presented in order to better understand the approach applicability and effectiveness.

[1]  Edward A. Lee,et al.  Modeling Cyber–Physical Systems , 2012, Proceedings of the IEEE.

[2]  M. A. Mohamed,et al.  FPGA Synthesis of VHDL OFDM System , 2013, Wirel. Pers. Commun..

[3]  Franco Fummi,et al.  UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration , 2013, IEEE Transactions on Computers.

[4]  Chen Xi,et al.  Modeling SystemC design in UML and automatic code generation , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[5]  Bente Anda,et al.  Applying use cases to design versus validate class diagrams - a controlled experiment using a professional modeling tool , 2003, 2003 International Symposium on Empirical Software Engineering, 2003. ISESE 2003. Proceedings..

[6]  P. S. Thiagarajan,et al.  Model-driven SoC design via executable UML to SystemC , 2004, 25th IEEE International Real-Time Systems Symposium.

[7]  Doo-Hwan Bae,et al.  Test cases generation from UML state diagrams , 1999, IEE Proc. Softw..

[8]  A. Hammad,et al.  Transformation of SysML Structure Diagrams to VHDL-AMS , 2012, 2012 Second Workshop on Design, Control and Software Implementation for Distributed MEMS.

[9]  V. Chaiyakul,et al.  Essential issues for IP reuse , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[10]  Franco Fummi,et al.  Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions , 2011, IEEE Transactions on Computers.

[11]  Cris Kobryn,et al.  Modeling enterprise software architectures using UML , 1998, Proceedings Second International Enterprise Distributed Object Computing (Cat. No.98EX244).

[12]  Elvinia Riccobene,et al.  A SoC design methodology involving a UML 2.0 profile for SystemC , 2005, Design, Automation and Test in Europe.

[13]  Ramon R. H. Schiffelers,et al.  Foundations of a Compositional Interchange Format for Hybrid Systems , 2007, HSCC.

[14]  M. Smith.  Graphical modelling and design with automatic code generation , 1995 .

[15]  Franco Fummi,et al.  HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels , 2012, Des. Autom. Embed. Syst..

[16]  Franco Fummi,et al.  HIFSuite: Tools for HDL Code Conversion and Manipulation , 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).

[17]  N. Harding.  A real time Java UML 2.0 profile , 2004 .

[18]  Fernando Herrera,et al.  Systemic Embedded Software Generation from SystemC , 2003, DATE.

[19]  Franco Fummi,et al.  Abstraction of RTL IPs into embedded software , 2010, Design Automation Conference.

[20]  Wim Dehaene,et al.  UML for electronic systems design: a comprehensive overview , 2008, Des. Autom. Embed. Syst..

[21]  W. Gareth J. Howells,et al.  A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL , 2008, IEEE Transactions on Computers.

[22]  Emad Samuel Malki Ebeid,et al.  On the Reuse of RTL IPs for SysML Model Generation , 2012, 2012 13th International Workshop on Microprocessor Test and Verification (MTV).

[23]  Da He,et al.  The SATURN Approach to SysML-Based HW/SW Codesign , 2010, ISVLSI.

[24]  Sofiène Tahar,et al.  Design and verification of SystemC transaction-level models , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Daniel D. Gajski,et al.  Embedded tutorial: essential issues for IP reuse , 2000, ASP-DAC '00.

[26]  David J. Greaves,et al.  Using RTL-to-C++ translation for large soc concurrent engineering: a case study , 2003 .

[27]  Kendall Scott,et al.  UML distilled - a brief guide to the Standard Object Modeling Language (2. ed.) , 2000, notThenot Addison-Wesley object technology series.

[28]  Franco Fummi,et al.  A Smooth Refinement Flow for Co-designing HW and SW Threads , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.