论文信息 - Modeling Latch-Up in CMOS Integrated Circuits

Modeling Latch-Up in CMOS Integrated Circuits

Latch-up is a common problem in CMOS integrated circuits. The modeling of latch-up with circuit simulation programs is addressed in this paper. The general features of a lumped element latch-up model are discussed along with a step-by-step approach to the component determination of the model. An example is presented to show the value of the latch-up model in latch-up threshold prediction. Finally, some latch-up control methods are discussed.

Robert W. Dutton | Donald B. Estreich | R. Dutton | D. Estreich

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