CDMA as a multiprocessor interconnect strategy

A binary CDMA bus is proposed as a communications interconnect for multiprocessor systems. The binary CDMA bus is a digital bus which incorporates spread-spectrum technology to encode multiple data streams in parallel onto the same physical interconnect. Mean value analysis is used to show that, for resource bandwidth-limited applications, the binary CDMA bus can deliver a throughput speedup over a split-transaction bus as large numbers of processors are interconnected, giving more scalable performance without additional end-to-end physical bus links. By monitoring bus utilization, the binary CDMA bus can be dynamically activated to alleviate contention and queueing delays experienced by a conventional bus. The inherently parallel access of the bus makes it useful for streaming data in DSP applications.

[1]  Takafumi Aoki,et al.  An efficient data transmission technique for VLSI systems based on multiple-valued code-division multiple access , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[2]  T. Matsuoka,et al.  DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[3]  Jr. Earl E. Swartzlander,et al.  VLSI Signal Processing Systems , 1985 .

[4]  M.-C. Chiang,et al.  Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment , 1992, IEEE Trans. Computers.

[5]  Paul M. Wexelblat An alternative addressing scheme for conventional CDMA fiber-optic networks allows interesting parallel processing capabilities , 1996, Proceedings of 1996 International Conference on Parallel and Distributed Systems.

[6]  Juan Carlos Herrero CDMA and TDMA based neural nets , 2000, Proceedings. Vol.1. Sixth Brazilian Symposium on Neural Networks.

[7]  E.E. Swartzlander,et al.  VLSI, MCM, and WSI: A Design Comparison , 1998, IEEE Des. Test Comput..

[8]  Earl E. Swartzlander A WSI macrocell fault circumvention strategy , 1991, 1991 Proceedings, International Conference on Wafer Scale Integration.