A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

An asynchronous pipeline scheme that combines a low power static circuit with a high-speed dual-rail dynamic circuit is proposed. The scheme utilizes a dual-rail circuit only in the critical path of an SRT division and square root calculation unit. The proposed implementation of the calculation unit reduced power consumption by more than 1/2 of the full-dynamic implementation while maintaining the calculation speed. Because of the elimination of spurious transitions, the proposed implementation showed even less power consumption over synchronous static circuit implementations. By using 0.3 /spl mu/m triple metal CMOS technology, the calculation time of floating point 56-b full mantissa division and square root is expected to be 45 ns in the worst case.

[1]  Tomás Lang,et al.  On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.

[2]  J. Mori,et al.  A 320 Mflops Cmos Floating-point Processing Unit For Superscalar Processors , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[3]  Gensoh Matsubara,et al.  30-ns 55-b shared radix 2 division and square root using a self-timed circuit , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[4]  S. Suzuki,et al.  A 500 MHz 1-stage 32 bit ALU with self-running test circuit , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[5]  Mark Horowitz,et al.  A zero-overhead self-timed 160-ns 54-b CMOS divider , 1991 .

[6]  L. Heller,et al.  Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Jan Fandrianto.  Algorithm for high speed shared radix 4 division and radix 4 square-root , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[8]  James E. Robertson,et al.  A New Class of Digital Division Methods , 1958, IRE Trans. Electron. Comput..

[9]  Marc Renaudin,et al.  A new asynchronous pipeline scheme: application to the design of a self-timed ring divider , 1996 .