IP core design of harmonic detection algorithm for power system

A large number of data operations in the common power system harmonic detection algorithm lead to master CPU run slower, which affects the accuracy and real-time performance of harmonic detection. A harmonic detection algorithm based on IP kernel is proposed. Under the condition that the data operation function of the original algorithm remains unchanged, this method completes the power system harmonic data analysis and processing operation by replacing the traditional main control CPU software program through the hardware logic unit, and solidifies the generated hardware description language file (VHDL) into the programmable logic device (FPGA) to create the IP core of the specific functions. Finally, the time taken by this method to process the same set of harmonic data is compared with the traditional software method. The results show that the method is effective and real-time.