Distribution of Class Codes in Moore FSMs

Chapter deals with optimization of logic circuits of Moore FSMs based on using two and three sources of codes of classes of pseudoequivalent states (PES). First of all, the application of this method for CPLD-based FSMs is discussed. Next, the models with two sources of class codes are discussed and corresponding design methods are proposed. This approach requires the usage of a multiplexor to choose a particular source. Also, the models with three sources of class codes are discussed and corresponding design methods are proposed. It is shown how the replacement of logical conditions can be used in multisource models of FSMs. At last, it is shown that the hardware reduction can be obtained due to increasing the number of class variables.

[1]  A. A. Barkalov.  Principles of logic optimization for a moore microprogrammed automaton , 1998 .

[2]  Alexander Barkalov,et al.  Hardware Reduction in FPGA-Based Moore FSM , 2013, J. Circuits Syst. Comput..

[3]  Dariusz Kania,et al.  Finite State Machine Logic Synthesis for Complex Programmable Logic Devices , 2013 .

[5]  C. Silvano,et al.  Low-power state assignment techniques for finite state machines , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[6]  S. Chmielewski,et al.  Optimization of Moore FSM on system-on-chip using PAL technology , 2008, 2008 International Conference on "Modern Problems of Radio Engineering, Telecommunications and Computer Science" (TCSET).

[7]  Alexander Barkalov,et al.  Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM , 2007, Int. J. Appl. Math. Comput. Sci..

[8]  S. Chmielewski,et al.  Optimization of Moore control unit with refined state encoding , 2008, 2008 15th International Conference on Mixed Design of Integrated Circuits and Systems.