A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs
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G. Gildenblat | G.D.J. Smit | D.B.M. Klaassen | Xin Li | A.J. Scholten | W. Wu | G.O. Workman | S. Veeraraghavan | C.C. McAndrew | R. van Langevelde | C. McAndrew | D. Klaassen | G. Gildenblat | S. Veeraraghavan | G. Workman | G. Smit | A. Scholten | R. Van Langevelde | W. Wu | Xin Li
[1] D.B.M. Klaassen,et al. Gate current: Modeling, /spl Delta/L extraction and impact on RF performance , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[2] Rajiv V. Joshi,et al. PD/SOI SRAM performance in presence of gate-to-body tunneling current , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[3] C. C. McAndrew,et al. An improved MOSFET model for circuit simulation , 1998 .
[4] G. Gildenblat,et al. Symmetric bulk charge linearisation in charge-sheet MOSFET model , 2001 .
[5] Chun-Yen Chang,et al. Impacts of gate structure on dynamic threshold SOI nMOSFETs , 2002, IEEE Electron Device Letters.
[6] Shiao-Shien Chen,et al. Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices , 2004, IEEE Transactions on Electron Devices.
[7] W. Grabinski,et al. RF distortion analysis with compact MOSFET models , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).
[8] Xin Li,et al. SP-SOI: a third generation surface potential based compact SOI MOSFET Model , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[9] G.D.J. Smit,et al. A new compact model for junctions in advanced CMOS technologies , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[10] C. Chuang,et al. Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits , 2002, 2002 IEEE International SOI Conference.
[11] G. Gildenblat,et al. Quasi-static and nonquasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges , 2003 .
[12] Gennady Gildenblat,et al. SP: an advanced surface-potential-based compact MOSFET model , 2003, IEEE Journal of Solid-State Circuits.
[13] Pin Su,et al. Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD , 2002, Proceedings International Symposium on Quality Electronic Design.
[14] C.C. McAndrew,et al. Validation of MOSFET model Source–Drain Symmetry , 2006, IEEE Transactions on Electron Devices.
[15] Jin Cai,et al. Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors , 2001 .
[16] G. Gildenblat,et al. Introduction to PSP MOSFET Model , 2005 .
[17] R. Puri,et al. Effects of gate-to-body tunneling current on PD/SOI CMOS latches , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..
[18] Ji-Woon Yang,et al. A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits , 2004 .
[19] C. Hu,et al. BSIM4 gate leakage model including source-drain partition , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[20] K. Mistry,et al. A general partition scheme for gate leakage current suitable for MOSFET compact models , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[21] Rajiv V. Joshi,et al. Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[22] G. Gildenblat,et al. A surface potential-based compact model of n-MOSFET gate-tunneling current , 2004, IEEE Transactions on Electron Devices.