Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs

In this paper a digitally-assisted foreground-liked calibration technique is proposed for offset cancellation of the residue amplifiers in high-resolution analog-to-digital converters. Two amplifiers are used while are in turn corrected for offset error. When the first amplifier participates in residue amplification the second one is calibrated to be substituted in the main data path. Two analog comparators are used to decide accumulation with +1 or -1 step based on the offset direction, or stop the count process. The digital equivalent of the input offset is stored on a digital latch array and is translated to analog voltage using a 10-bit digital-to-analog converter. Counting treat of the accumulator is stopped when the loop enters to the lock state. Simulation results confirm that the input offset voltage of around 8mVolts is reduced to less than 20μVolts when the gain of the auxiliary amplifier is 60dB. The Monte-Carlo analysis shows that the input-referred offset is around 53μVolts at 1σ while was 4.8mVolts before cancellation. The remained offset is reduced to less than the half value of LSB amplitude in 14-bits ADC where the peak-to-peak range is 1600mVolts. Simulations are performed using the BSIM3 model of a 0.18μm CMOS technology.

[1]  Mau-Chung Frank Chang,et al.  A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  Bang-Sup Song,et al.  A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering , 2008, IEEE Journal of Solid-State Circuits.

[4]  H. Matsui,et al.  A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration , 2006, IEEE Journal of Solid-State Circuits.

[5]  Bang-Sup Song,et al.  A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming , 2000, IEEE Journal of Solid-State Circuits.

[6]  Hung-Chih Liu,et al.  A digital background calibration technique for pipelined analog-to-digital converters , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  Ian Galton,et al.  Digital Background Correction of Harmonic Distortion in Pipelined ADCs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Li Ding,et al.  A background amplifier offset calibration technique for high-resolution pipelined ADCs , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

[9]  S. Pavan,et al.  A Distortion Compensating Flash Analog-to-Digital Conversion Technique , 2006, IEEE Journal of Solid-State Circuits.

[10]  J. Bjornsen,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[11]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[12]  Bjørnar Hernes,et al.  A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS , 2005 .