A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations

Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing power supply voltage in scaled CMOS technologies. A seven-transistor (7T), an eight-transistor (8T), a nine-transistor (9T), and 3 conventional six-transistor (6T) memory circuits are characterized for layout area, data stability, write voltage margin, data access speed, active power consumption, idle mode leakage currents, and minimum power supply voltage in this paper. A comprehensive electrical performance metric is evaluated to compare the memory cells considering process parameter and supply voltage fluctuations. The triple-threshold-voltage 8T and 9T SRAM cells provide up to 2.5× stronger data stability and 765.9× higher overall electrical quality as compared to the traditional 6T SRAM cells in a TSMC 65 nm CMOS technology.

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