Leakage current control of nano-scale full adder cells using input vectors

As CMOS technology scaling continues into the nanoscale domain, static or leakage power consumption becomes a vital design parameter. This paper proposes methods for reducing leakage currents by controlling the input vector in nano-scale full adder cells operating in either active mode or standby mode. With proper input vector control, it is possible to obtain over 40% leakage power savings for most of the full adder circuits presented.

[1]  Yuke Wang,et al.  Design and analysis of 10-transistor full adders using novel XOR-XNOR gates , 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

[2]  Magdy A. Bayoumi,et al.  A new full adder cell for low-power applications , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[3]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[4]  Richard B. Brown,et al.  Efficient techniques for gate leakage estimation , 2003, ISLPED '03.

[5]  Massoud Pedram,et al.  Leakage current reduction in CMOS VLSI circuits by input vector control , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[7]  Gerald E. Sobelman,et al.  A new low-voltage full adder circuit , 1997, Proceedings Great Lakes Symposium on VLSI.

[8]  Wang Ling,et al.  A novel 10-transistor low-power high-speed full adder cell , 2001, 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443).

[9]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.