PROCESSOR ALLOCATOR FOR CHIP MULTIPROCESSORS

[1]  Chita R. Das,et al.  A low latency router supporting adaptivity for on-chip interconnects , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[2]  Ten-Hwang Lai,et al.  Processor Job Scheduling Is More Important than Allocation for Hypercube Computers , 1994 .

[3]  Leslie G. Valiant,et al.  Universal schemes for parallel communication , 1981, STOC '81.

[4]  Lu Zhang.  Comments on "A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers" , 2003, IEEE Trans. Computers.

[5]  P. Merlin,et al.  Deadlock Avoidance in Store-and-Forward Networks - I: Store-and-Forward Deadlock , 1980, IEEE Transactions on Communications.

[6]  Pascal Theodoor Wolkotte,et al.  Exploration within the Network-on-Chip Paradigm , 2009 .

[7]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[8]  Amit Kumar,et al.  NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[9]  Lionel M. Ni,et al.  Efficient processor allocation for 3D tori , 1995, Proceedings of 9th International Parallel Processing Symposium.

[10]  Nian-Feng Tzeng,et al.  An efficient submesh allocation strategy for mesh computer systems , 1991, [1991] Proceedings. 11th International Conference on Distributed Computing Systems.

[11]  Dhiraj K. Pradhan,et al.  A fast and efficient strategy for submesh allocation in mesh-connected parallel computers , 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

[12]  Jih-Sheng Shen,et al.  Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Stephen W. Keckler,et al.  Scalable On-Chip Interconnect Topologies , 2008 .

[14]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[15]  George Ferizis,et al.  Mapping Recursive Functions to Reconfigurable Hardware , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[16]  Andrew A. Chien,et al.  Compressionless routing: a framework for adaptive and fault-tolerant routing , 1994, ISCA '94.

[17]  Li-Shiuan Peh,et al.  High-level power analysis for on-chip networks , 2004, CASES '04.

[18]  P.T. Wolkotte,et al.  Energy Model of Networks-on-Chip and a Bus , 2005, 2005 International Symposium on System-on-Chip.

[19]  Timothy Mark Pinkston,et al.  An efficient, fully adaptive deadlock recovery scheme: DISHA , 1995, ISCA.

[20]  Henry Selvaraj,et al.  Processor Allocation Problem for NoC-Based Chip Multiprocessors , 2009, 2009 Sixth International Conference on Information Technology: New Generations.

[21]  D. Grunwald,et al.  The Performance of Multicomputer Interconnection Networks , 1987, Computer.

[22]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[23]  Timothy Mark Pinkston,et al.  Characterization of Deadlocks in k-ary n-Cube Networks , 1999, IEEE Trans. Parallel Distributed Syst..

[24]  William J. Dally,et al.  Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels , 1993, IEEE Trans. Parallel Distributed Syst..

[25]  William J. Dally,et al.  Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.

[26]  Mani B. Srivastava,et al.  A survey of techniques for energy efficient on-chip communication , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[27]  William J. Dally,et al.  Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks , 1989, IEEE Trans. Computers.

[28]  Daniel Wiklund.  Development and performance evaluation of networks on chip , 2005 .

[29]  W. J. Dally,et al.  Finite-grain message passing concurrent computers , 1988, C3P.

[30]  César A. F. De Rose,et al.  Distributed dynamic processor allocation for multicomputers , 2007, Parallel Comput..

[31]  Yaagoub Ashir,et al.  Lee Distance and Topological Properties of k-ary n-cubes , 1995, IEEE Trans. Computers.

[32]  William J. Dally,et al.  Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[33]  S. Kambhatla.  Hypercube Vs Cube-Connected Cycles: A Topological Evaluation , 1991, The Sixth Distributed Memory Computing Conference, 1991. Proceedings.

[34]  Masaaki Oka,et al.  Designing and programming the emotion engine , 1999, IEEE Micro.

[35]  Yahui Zhu,et al.  Efficient Processor Allocation Strategie for Mesh-Connected Parallel Computers , 1992, J. Parallel Distributed Comput..

[36]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[37]  Franco P. Preparata,et al.  The cube-connected-cycles: A versatile network for parallel computation , 1979, 20th Annual Symposium on Foundations of Computer Science (sfcs 1979).

[38]  Martin Hopkins,et al.  Synergistic Processing in Cell's Multicore Architecture , 2006, IEEE Micro.

[39]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[40]  César A. F. De Rose,et al.  Dynamic Processor Allocation in Large Mesh-Connected Multicomputers , 2001, Euro-Par.

[41]  Chita R. Das,et al.  A Lazy Scheduling Scheme for Improving Hypercube Performance , 1993, 1993 International Conference on Parallel Processing - ICPP'93.

[42]  William J. Dally,et al.  The torus routing chip , 2005, Distributed Computing.

[43]  Henry Selvaraj,et al.  Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors , 2010, Microprocess. Microsystems.

[44]  William J. Dally,et al.  Flattened butterfly: a cost-efficient topology for high-radix networks , 2007, ISCA '07.

[45]  Hamid Sarbazi-Azad,et al.  The effect of virtual channel organization on the performance of interconnection networks , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[46]  Stephen W. Keckler,et al.  2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), 2008 , 2008 .

[47]  Hee Yong Youn,et al.  An efficient task allocation scheme for two-dimensional mesh-connected systems , 1995, Proceedings of 15th International Conference on Distributed Computing Systems.

[48]  Gerard J. M. Smit,et al.  Energy efficient NoC for best effort communication , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[49]  Phillip Krueger,et al.  ob Scheduling is More Important than Processor Allocation for Hypercube Computers , 1994, IEEE Trans. Parallel Distributed Syst..

[50]  Brent E. Nelson,et al.  A Parallel FFT Architecture for FPGAs , 2004, FPL.

[51]  Keith J. Burnham,et al.  Algorithms to Managing Unicast, Multicast and Broadcast Transmission for Optical Switches , 2008, APNOMS.

[52]  Wayne H. Wolf,et al.  Multiprocessor Systems-on-Chips , 2004, ISVLSI.

[53]  J DallyWilliam,et al.  Performance Analysis of k-ary n-cube Interconnection Networks , 1990 .

[54]  D. Jayasimha,et al.  On-Chip Interconnection Networks : Why They are Different and How to Compare Them , 2007 .

[55]  Iwona Pozniak-Koszalka,et al.  Algorithms of Unicast, Multicast and Broadcast Transmission for Optical Switches , 2007, Sixth International Conference on Networking (ICN'07).

[56]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[57]  Russell Tessier,et al.  An architecture and compiler for scalable on-chip communication , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[58]  Arun Kumar Reddy Toomu.  Pipelined implementation of Jpeg image compression using Hdl , 2008 .

[59]  Mohan Kumar,et al.  On generalized fat trees , 1995, Proceedings of 9th International Parallel Processing Symposium.

[60]  Saad Bani-Mohammad,et al.  Comparative evaluation of the non-contiguous processor allocation strategies based on a real workload and a stochastic workload on multicomputers , 2007, 2007 International Conference on Parallel and Distributed Systems.

[61]  Pinaki Mazumder,et al.  Evaluation of On-Chip Static Interconnection Networks , 1987, IEEE Transactions on Computers.

[62]  Gerard J. M. Smit,et al.  A virtual channel router for on-chip networks , 2004, IEEE International SOC Conference, 2004. Proceedings..

[63]  Chita R. Das,et al.  Processor Management Techniques for Mesh-Connected Multiprocessors , 1995, ICPP.

[64]  Laxmi N. Bhuyan,et al.  An Adaptive Submesh Allocation Strategy for Two-Dimensional Mesh Connected Systems , 1993, 1993 International Conference on Parallel Processing - ICPP'93.

[65]  Leonard Kleinrock,et al.  Virtual Cut-Through: A New Computer Communication Switching Technique , 1979, Comput. Networks.

[66]  N. Shlayan,et al.  Review of Packet Switching Technologies for Future NoC , 2008, 2008 19th International Conference on Systems Engineering.

[67]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[68]  Matt W. Mutka,et al.  Efficient job scheduling in a mesh multicomputer without discrimination against large jobs , 1995, Proceedings.Seventh IEEE Symposium on Parallel and Distributed Processing.

[69]  Theodore R. Bashkow,et al.  A large scale, homogeneous, fully distributed parallel machine, I , 1977, ISCA '77.

[70]  Chita R. Das,et al.  Efficient fully adaptive wormhole routing in n-dimensional meshes , 1994, 14th International Conference on Distributed Computing Systems.

[71]  Dror G. Feitelson,et al.  Improved Utilization and Responsiveness with Gang Scheduling , 1997, JSSPP.

[72]  Dhiraj K. Pradhan,et al.  Job Scheduling in Mesh Multicomputers , 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

[73]  Tong Liu,et al.  A Submesh Allocation Scheme for Mesh-Connected Multiprocessor Systems , 1995, ICPP.

[74]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[75]  Tarek A. El-Ghazawi,et al.  Performance of sorting algorithms on the SRC 6 reconfigurable computer , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[76]  William J. Dally,et al.  Flattened Butterfly Topology for On-Chip Networks , 2007, IEEE Comput. Archit. Lett..

[77]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1992, ISCA '92.

[78]  José Duato,et al.  A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks , 1993, IEEE Trans. Parallel Distributed Syst..

[79]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[80]  José E. Moreira,et al.  Job Scheduling for the BlueGene/L System , 2002, JSSPP.

[81]  Stephen B. Furber,et al.  An asynchronous on-chip network router with quality-of-service (QoS) support , 2004, IEEE International SOC Conference, 2004. Proceedings..

[82]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[83]  Timo Hämäläinen,et al.  Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC , 2006, EURASIP J. Embed. Syst..

[84]  Prasant Mohapatra,et al.  A Traffic-Balanced Adaptive Wormhole-Routing Scheme for Two-Dimensional Meshes , 1997, IEEE Trans. Computers.

[85]  Daniel H. Linder,et al.  An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-Ary n-Cubes , 1994, IEEE Trans. Computers.

[86]  Ten-Hwang Lai,et al.  Scheduling Independent Jobs on Partitionable Hypercubes , 1991, J. Parallel Distributed Comput..

[87]  Andrew A. Chien,et al.  Planar-adaptive routing: low-cost adaptive networks for multiprocessors , 1992, ISCA '92.

[88]  H. Zimmermann,et al.  OSI Reference Model - The ISO Model of Architecture for Open Systems Interconnection , 1980, IEEE Transactions on Communications.

[89]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[90]  Nikolay Kavaldjiev,et al.  A run-time reconfigurable Network-on-Chip for streaming DSP applications , 2006 .

[91]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[92]  Axel Jantsch,et al.  Networks on chip , 2003 .

[93]  Dror G. Feitelson,et al.  Utilization, Predictability, Workloads, and User Runtime Estimates in Scheduling the IBM SP2 with Backfilling , 2001, IEEE Trans. Parallel Distributed Syst..

[94]  Shreekant S. Thakkar,et al.  Multiprocessor Validation of the Pentium Pro , 1996, Computer.

[95]  Saurabh Dighe,et al.  An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[96]  Hyunsoo Yoon,et al.  On Submesh Allocation for Mesh Multicomputers: A Best-Fit Allocation and a Virtual Submesh Allocation for Faulty Meshes , 1998, IEEE Trans. Parallel Distributed Syst..

[97]  Luca Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, DAC '02.

[98]  Prasant Mohapatra,et al.  An integrated processor management scheme for the mesh-connected multicomputer systems , 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).

[99]  Po-Jen Chuang,et al.  An Efficient Recognition-Complete Processor Allocation Strategy for k-ary n-cube Multiprocessors , 2000, IEEE Trans. Parallel Distributed Syst..

[100]  José Duato,et al.  Generalized theory for deadlock-free adaptive wormhole routing and its application to Disha Concurrent , 1996, Proceedings of International Conference on Parallel Processing.

[101]  Guy Lemieux,et al.  The NUMAchine multiprocessor , 2000, Proceedings 2000 International Conference on Parallel Processing.

[102]  Kang G. Shin,et al.  Adaptive Deadlock-Free Routing in Multicomputers Using Only One Extra Virtual Channel , 1993, 1993 International Conference on Parallel Processing - ICPP'93.

[103]  Ismail Ababneh.  An efficient free-list submesh allocation scheme for two-dimensional mesh-connected multicomputers , 2006, J. Syst. Softw..

[104]  Heikki Kariniemi,et al.  On-line reconfigurable extended generalized fat tree network-on-chip for multiprocessor system-on-chip circuits , 2006 .

[105]  Gian Carlo Cardarilli,et al.  Power characterization of digital filters implemented on FPGA , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[106]  Chung-Ta King,et al.  Dynamic processor allocation in scalable multiprocessors using boolean algebra , 1998, Int. J. Comput. Math..

[107]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[108]  Jens Sparsø,et al.  The MANGO clockless network-on-chip: Concepts and implementation , 2006 .

[109]  Chita R. Das,et al.  A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers , 2002, IEEE Trans. Computers.

[110]  Stephan Bourduas,et al.  Modeling, Evaluation, and Implementation of Ring-Based Interconnects for Network-on-Chip , 2008 .

[111]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[112]  M. Suzuoki,et al.  Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor , 2006, IEEE Journal of Solid-State Circuits.

[113]  M.-C. Chiang,et al.  Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment , 1992, IEEE Trans. Computers.

[114]  Dhiraj K. Pradhan,et al.  Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation , 1995, IEEE Trans. Parallel Distributed Syst..

[115]  Henry Selvaraj,et al.  Fast and efficient processor allocation algorithm for torus-based chip multiprocessors , 2011, Comput. Electr. Eng..

[116]  J. Kim,et al.  A Top-Down Processor Allocation Scheme for Hypercube Computers , 1991, IEEE Trans. Parallel Distributed Syst..

[117]  Sudhakar Yalamanchili,et al.  Interconnection Networks , 2011, Encyclopedia of Parallel Computing.

[118]  Niraj K. Jha,et al.  Express virtual channels: towards the ideal interconnection fabric , 2007, ISCA '07.