A DC-20GHz CMOS active power divider design

We report the design of a wideband active power divider using commercial CMOS process. This circuit is made of two distributed amplifiers sharing a common input artificial transmission line while two distinct transmission lines are employed for the output ports. Since the input transmission line tends to be overly capacitive now when compared with the conventional distributed amplifier, the constituting gain cells need to be revised so as to retain the intended 20GHz bandwidth. Small input and output reflection coefficients have been observed, and the measured output port isolation is below −30dB across the whole bandwidth, which is beyond the reach of passive power dividers. Magnitude and phase imbalances of the two output ports are 0.2dB and 0.4° at 15GHz, and 0.9dB and 0.6° at 20GHz. The noise figure is 6.9dB at 15GHz and 9.4dB at 20GHz. The input-referred 1dB compression point is −9.5dBm at 15GHz and −10.5dBm at 20GHz. With the bias of 2.5Volt and 64Amp, the total power dissipation is 160mWatt.